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99b0d285 WD |
1 | /* |
2 | * Rick Bronson <rick@efn.org> | |
3 | * | |
4 | * Configuation settings for the AT91RM9200DK board. | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
26 | * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005 | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
32 | /* ARM asynchronous clock */ | |
33 | #define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */ | |
34 | #define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ | |
35 | ||
36 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | |
37 | ||
38 | #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ | |
39 | #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ | |
40 | /* Only define one of the following, based on board type */ | |
41 | /* #define CONFIG_KB9200 1 KwikByte KB9202 board */ | |
42 | /* #define CONFIG_KB9201 1 KwikByte KB9202 board */ | |
43 | #define CONFIG_KB9202 1 /* KwikByte KB9202 board */ | |
44 | ||
45 | #define CONFIG_KB920x 1 /* Any KB920x board */ | |
46 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
47 | #define USE_920T_MMU 1 | |
48 | ||
49 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
50 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
51 | #define CONFIG_INITRD_TAG 1 | |
52 | ||
53 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
8052352f JS |
54 | #define CONFIG_SKIP_RELOCATE_UBOOT /* undef this for direct boot from */ |
55 | /* NOR flash without preloader */ | |
99b0d285 | 56 | |
6d0f6bcf | 57 | #define CONFIG_SYS_LONGHELP |
99b0d285 | 58 | |
b83dcc13 WD |
59 | #ifndef roundup |
60 | #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) | |
61 | #endif | |
99b0d285 WD |
62 | /* |
63 | * Size of malloc() pool | |
64 | */ | |
6d0f6bcf JCPV |
65 | #define CONFIG_SYS_MALLOC_LEN (roundup(CONFIG_ENV_SIZE,4096) + 128*1024) |
66 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
99b0d285 WD |
67 | |
68 | #define CONFIG_BAUDRATE 115200 | |
69 | ||
70 | /* | |
71 | * Hardware drivers | |
72 | */ | |
73 | ||
74 | /* define one of these to choose the DBGU, USART0 or USART1 as console */ | |
75 | #define CONFIG_DBGU | |
76 | #undef CONFIG_USART0 | |
77 | #undef CONFIG_USART1 | |
78 | ||
79 | #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ | |
80 | ||
81 | #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ | |
82 | ||
83 | #define CONFIG_BOOTDELAY 3 | |
84 | #define CONFIG_ENV_OVERWRITE 1 | |
85 | ||
bc234c12 | 86 | |
7f5c0157 JL |
87 | /* |
88 | * BOOTP options | |
89 | */ | |
90 | #define CONFIG_BOOTP_BOOTFILESIZE | |
91 | #define CONFIG_BOOTP_BOOTPATH | |
92 | #define CONFIG_BOOTP_GATEWAY | |
93 | #define CONFIG_BOOTP_HOSTNAME | |
94 | ||
95 | ||
bc234c12 JL |
96 | /* |
97 | * Command line configuration. | |
98 | */ | |
99 | #include <config_cmd_default.h> | |
100 | ||
101 | #define CONFIG_CMD_I2C | |
102 | #define CONFIG_CMD_PING | |
103 | #define CONFIG_CMD_DHCP | |
104 | ||
105 | #undef CONFIG_CMD_BDI | |
106 | #undef CONFIG_CMD_FPGA | |
107 | #undef CONFIG_CMD_MISC | |
108 | ||
99b0d285 WD |
109 | |
110 | #define CONFIG_NR_DRAM_BANKS 1 | |
111 | #define PHYS_SDRAM 0x20000000 | |
112 | #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ | |
113 | ||
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
115 | #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024) | |
99b0d285 WD |
116 | |
117 | #define CONFIG_DRIVER_ETHER | |
118 | #define CONFIG_NET_RETRY_COUNT 20 | |
119 | ||
6d0f6bcf | 120 | #define CONFIG_SYS_FLASH_BASE 0x10000000 |
99b0d285 WD |
121 | |
122 | #ifdef CONFIG_KB9202 | |
123 | #define PHYS_FLASH_SIZE 0x1000000 | |
124 | #else | |
125 | #define PHYS_FLASH_SIZE 0x200000 | |
126 | #endif | |
127 | ||
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
129 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
99b0d285 WD |
130 | |
131 | #define CONFIG_HARD_I2C | |
132 | ||
bb1f8b4f | 133 | #define CONFIG_ENV_IS_IN_EEPROM |
99b0d285 WD |
134 | |
135 | #ifdef CONFIG_KB9202 | |
0e8d1586 JCPV |
136 | #define CONFIG_ENV_OFFSET 0x3E00 |
137 | #define CONFIG_ENV_SIZE 0x0200 | |
99b0d285 | 138 | #else |
0e8d1586 JCPV |
139 | #define CONFIG_ENV_OFFSET 0x1000 |
140 | #define CONFIG_ENV_SIZE 0x1000 | |
99b0d285 | 141 | #endif |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
143 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
144 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
145 | #define CONFIG_SYS_I2C_SPEED 50000 | |
146 | #define CONFIG_SYS_I2C_SLAVE 0 /* not used */ | |
147 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
99b0d285 | 148 | |
6d0f6bcf | 149 | #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ |
99b0d285 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
99b0d285 | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */ |
154 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
155 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
156 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
99b0d285 | 157 | |
00b1883a | 158 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf | 159 | #define CONFIG_SYS_FLASH_CFI |
99b0d285 WD |
160 | |
161 | #ifndef __ASSEMBLY__ | |
162 | /*----------------------------------------------------------------------- | |
163 | * Board specific extension for bd_info | |
164 | * | |
165 | * This structure is embedded in the global bd_info (bd_t) structure | |
166 | * and can be used by the board specific code (eg board/...) | |
167 | */ | |
168 | ||
169 | struct bd_info_ext { | |
170 | /* helper variable for board environment handling | |
171 | * | |
172 | * env_crc_valid == 0 => uninitialised | |
173 | * env_crc_valid > 0 => environment crc in flash is valid | |
174 | * env_crc_valid < 0 => environment crc in flash is invalid | |
175 | */ | |
176 | int env_crc_valid; | |
177 | }; | |
178 | #endif | |
179 | ||
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_HZ 1000 |
181 | #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ | |
99b0d285 WD |
182 | /* AT91C_TC_TIMER_DIV1_CLOCK */ |
183 | ||
184 | #define CONFIG_STACKSIZE (32*1024) /* regular stack */ | |
185 | ||
186 | #ifdef CONFIG_USE_IRQ | |
187 | #error CONFIG_USE_IRQ not supported | |
188 | #endif | |
189 | ||
190 | #endif |