[people/ms/u-boot.git] / include / configs / km / km83xx-common.h

/*
 * (C) Copyright 2010
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#ifndef __CONFIG_KM83XX_H
#define __CONFIG_KM83XX_H

/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#include "km-powerpc.h"

#ifndef MTDIDS_DEFAULT
# define MTDIDS_DEFAULT	"nor0=boot"
#endif /* MTDIDS_DEFAULT */

#ifndef MTDPARTS_DEFAULT
# define MTDPARTS_DEFAULT	"mtdparts="			\
	"boot:"							\
		"768k(u-boot),"					\
		"128k(env),"					\
		"128k(envred),"					\
		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
#endif /* MTDPARTS_DEFAULT */

#define CONFIG_MISC_INIT_R
/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN		66000000
#define CONFIG_SYS_CLK_FREQ		66000000
#define CONFIG_83XX_PCICLK		66000000

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * Bus Arbitration Configuration Register (ACR)
 */
#define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
#define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
#define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
#define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */

#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)

#define CFG_83XX_DDR_USES_CS0

/*
 * Manually set up DDR parameters
 */
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE		2048 /* MB */

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE		0xF0000000

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

/* Reserve 768 kB for Mon */
#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)

/*
 * Init Local Bus Memory Controller:
 *
 * Bank Bus     Machine PortSz  Size  Device
 * ---- ---     ------- ------  -----  ------
 *  0   Local   GPCM    16 bit  256MB FLASH
 *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 *
 */
/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
				BR_PS_16 | /* 16 bit port size */ \
				BR_MS_GPCM | /* MSEL = GPCM */ \
				BR_V)

#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
				OR_GPCM_SCY_5 | \
				OR_GPCM_TRLX_SET | OR_GPCM_EAD)

#define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

/*
 * PRIO1/PIGGY on the local bus CS1
 */
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_KMBEC_FPGA_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128MB)

#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_KMBEC_FPGA_BASE | \
				BR_PS_8 | /* 8 bit port size */ \
				BR_MS_GPCM | /* MSEL = GPCM */ \
				BR_V)
#define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
				OR_GPCM_SCY_2 | \
				OR_GPCM_TRLX_SET | OR_GPCM_EAD)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"UEC0"

#if !defined(CONFIG_MPC8309)
#define CONFIG_UEC_ETH1		/* GETH1 */
#define UEC_VERBOSE_DEBUG	1
#endif

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif

/*
 * Environment
 */

#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
					CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#else /* CFG_SYS_RAMBOOT */
#define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE		0x2000
#endif /* CFG_SYS_RAMBOOT */

/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C_SPEED	200000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE	0x7F
#define CONFIG_SYS_I2C_OFFSET	0x3000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS		1
#define CONFIG_I2C_MUX

/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75		/* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS	{0, 1, 2, 3}	/* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define CONFIG_SYS_DTT_HYSTERESIS	3
#define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)

#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
#endif

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT		0x000000000
#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
					 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2			HID2_HBE

/*
 * MMU Setup
 */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
					| BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
				BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
				BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U

/*
 * Internal Definitions
 */
#define BOOTFLASH_START	0xF0000000

#define CONFIG_KM_CONSOLE_TTY	"ttyS0"

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif

#ifndef CONFIG_KM_DEF_ARCH
#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
#endif

#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_KM_DEF_ENV						\
	CONFIG_KM_DEF_ARCH						\
	"EEprom_ivm=pca9547:70:9\0"					\
	"newenv="							\
		"prot off 0xF00C0000 +0x40000 && "			\
		"era 0xF00C0000 +0x40000\0"				\
	"unlock=yes\0"							\
	""

#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#endif

#endif /* __CONFIG_KM83XX_H */
Commit	Line	Data
62ddcf05 HS	1	/*
	2	* (C) Copyright 2010
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*/
	10
	11	#ifndef __CONFIG_KM83XX_H
	12	#define __CONFIG_KM83XX_H
	13
	14	/* include common defines/options for all Keymile boards */
	15	#include "keymile-common.h"
	16	#include "km-powerpc.h"
	17
cf73639d AH	18	#ifndef MTDIDS_DEFAULT
	19	# define MTDIDS_DEFAULT "nor0=boot"
	20	#endif /* MTDIDS_DEFAULT */
	21
	22	#ifndef MTDPARTS_DEFAULT
	23	# define MTDPARTS_DEFAULT "mtdparts=" \
62ddcf05 HS	24	"boot:" \
	25	"768k(u-boot)," \
	26	"128k(env)," \
	27	"128k(envred)," \
cf73639d AH	28	"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
cf73639d AH	29	#endif /* MTDPARTS_DEFAULT */
62ddcf05 HS	30
	31	#define CONFIG_MISC_INIT_R
	32	/*
	33	* System Clock Setup
	34	*/
	35	#define CONFIG_83XX_CLKIN 66000000
	36	#define CONFIG_SYS_CLK_FREQ 66000000
	37	#define CONFIG_83XX_PCICLK 66000000
	38
	39	/*
	40	* IMMR new address
	41	*/
	42	#define CONFIG_SYS_IMMR 0xE0000000
	43
	44	/*
	45	* Bus Arbitration Configuration Register (ACR)
	46	*/
	47	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
	48	#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
	49	#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
	50	#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
	51
	52	/*
	53	* DDR Setup
	54	*/
	55	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
	56	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
0f2b721c HB	57	#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
0f2b721c HB	58
62ddcf05 HS	59	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	60	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \| \
	61	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
	62
	63	#define CFG_83XX_DDR_USES_CS0
	64
	65	/*
	66	* Manually set up DDR parameters
	67	*/
	68	#define CONFIG_DDR_II
	69	#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
	70
	71	/*
	72	* The reserved memory
	73	*/
	74	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	75	#define CONFIG_SYS_FLASH_BASE 0xF0000000
	76
	77	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	78	#define CONFIG_SYS_RAMBOOT
	79	#endif
	80
	81	/* Reserve 768 kB for Mon */
	82	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
	83
	84	/*
	85	* Initial RAM Base Address Setup
	86	*/
	87	#define CONFIG_SYS_INIT_RAM_LOCK
	88	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	89	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
	90	#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
	91	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	92	GENERATED_GBL_DATA_SIZE)
	93
	94	/*
	95	* Init Local Bus Memory Controller:
	96	*
	97	* Bank Bus Machine PortSz Size Device
	98	* ---- --- ------- ------ ----- ------
	99	* 0 Local GPCM 16 bit 256MB FLASH
	100	* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
	101	*
	102	*/
	103	/*
	104	* FLASH on the Local Bus
	105	*/
	106	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
	107	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
	108	#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
	109	#define CONFIG_SYS_FLASH_PROTECTION
	110	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	111
	112	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	113	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_256MB)
62ddcf05 HS	114
62ddcf05 HS	115	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
7d6a0982 JH	116	BR_PS_16 \| /* 16 bit port size */ \
7d6a0982 JH	117	BR_MS_GPCM \| /* MSEL = GPCM */ \
62ddcf05 HS	118	BR_V)
	119
	120	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \| \
	121	OR_GPCM_CSNT \| OR_GPCM_ACS_DIV2 \| \
	122	OR_GPCM_SCY_5 \| \
7d6a0982	123	OR_GPCM_TRLX_SET \| OR_GPCM_EAD)
62ddcf05 HS	124
	125	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	126	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	127	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	128
	129	/*
	130	* PRIO1/PIGGY on the local bus CS1
	131	*/
8ed74341 HS	132	/* Window base at flash base */
8ed74341 HS	133	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
7d6a0982	134	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_128MB)
62ddcf05	135
8ed74341	136	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE \| \
7d6a0982 JH	137	BR_PS_8 \| /* 8 bit port size */ \
7d6a0982 JH	138	BR_MS_GPCM \| /* MSEL = GPCM */ \
62ddcf05	139	BR_V)
8ed74341	140	#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) \| \
62ddcf05 HS	141	OR_GPCM_CSNT \| OR_GPCM_ACS_DIV2 \| \
62ddcf05 HS	142	OR_GPCM_SCY_2 \| \
7d6a0982	143	OR_GPCM_TRLX_SET \| OR_GPCM_EAD)
62ddcf05 HS	144
	145	/*
	146	* Serial Port
	147	*/
	148	#define CONFIG_CONS_INDEX 1
	149	#define CONFIG_SYS_NS16550
	150	#define CONFIG_SYS_NS16550_SERIAL
	151	#define CONFIG_SYS_NS16550_REG_SIZE 1
	152	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	153
	154	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	155	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
	156
	157	/* Pass open firmware flat tree */
	158	#define CONFIG_OF_LIBFDT
	159	#define CONFIG_OF_BOARD_SETUP
	160	#define CONFIG_OF_STDOUT_VIA_ALIAS
	161
62ddcf05 HS	162	/*
	163	* QE UEC ethernet configuration
	164	*/
	165	#define CONFIG_UEC_ETH
	166	#define CONFIG_ETHPRIME "UEC0"
	167
5bcd64cf	168	#if !defined(CONFIG_MPC8309)
62ddcf05 HS	169	#define CONFIG_UEC_ETH1 /* GETH1 */
62ddcf05 HS	170	#define UEC_VERBOSE_DEBUG 1
5bcd64cf	171	#endif
62ddcf05 HS	172
	173	#ifdef CONFIG_UEC_ETH1
	174	#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
	175	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
	176	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
	177	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	178	#define CONFIG_SYS_UEC1_PHY_ADDR 0
	179	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
	180	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
	181	#endif
	182
	183	/*
	184	* Environment
	185	*/
	186
	187	#ifndef CONFIG_SYS_RAMBOOT
	188	#define CONFIG_ENV_IS_IN_FLASH
	189	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	190	CONFIG_SYS_MONITOR_LEN)
	191	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	192	#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
	193
	194	/* Address and size of Redundant Environment Sector */
	195	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	196	CONFIG_ENV_SECT_SIZE)
	197	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	198
	199	#else /* CFG_SYS_RAMBOOT */
	200	#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
	201	#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
	202	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	203	#define CONFIG_ENV_SIZE 0x2000
	204	#endif /* CFG_SYS_RAMBOOT */
	205
	206	/* I2C */
	207	#define CONFIG_HARD_I2C /* I2C with hardware support */
	208	#define CONFIG_FSL_I2C
	209	#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
	210	#define CONFIG_SYS_I2C_SLAVE 0x7F
	211	#define CONFIG_SYS_I2C_OFFSET 0x3000
ea818dbb HS	212	#define CONFIG_I2C_MULTI_BUS
	213	#define CONFIG_SYS_MAX_I2C_BUS 1
	214	#define CONFIG_I2C_MUX
62ddcf05 HS	215
	216	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	217	#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
	218	#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
	219	#define CONFIG_SYS_DTT_MAX_TEMP 70
	220	#define CONFIG_SYS_DTT_LOW_TEMP -30
	221	#define CONFIG_SYS_DTT_HYSTERESIS 3
	222	#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
	223
	224	#if defined(CONFIG_CMD_NAND)
	225	#define CONFIG_NAND_KMETER1
	226	#define CONFIG_SYS_MAX_NAND_DEVICE 1
8ed74341	227	#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
62ddcf05 HS	228	#endif
	229
	230	#if defined(CONFIG_PCI)
	231	#define CONFIG_CMD_PCI
	232	#endif
	233
	234	/*
	235	* For booting Linux, the board info and command line data
	236	* have to be in the first 8 MB of memory, since this is
	237	* the maximum mapped by the Linux kernel during initialization.
	238	*/
	239	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
	240
	241	/*
	242	* Core HID Setup
	243	*/
	244	#define CONFIG_SYS_HID0_INIT 0x000000000
	245	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	246	HID0_ENABLE_INSTRUCTION_CACHE)
	247	#define CONFIG_SYS_HID2 HID2_HBE
	248
	249	/*
	250	* MMU Setup
	251	*/
	252
	253	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	254
	255	/* DDR: cache cacheable */
72cd4087	256	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \
62ddcf05 HS	257	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	258	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| \
	259	BATU_VS \| BATU_VP)
	260	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	261	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	262
	263	/* IMMRBAR & PCI IO: cache-inhibit and guarded */
72cd4087	264	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \
62ddcf05 HS	265	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	266	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \| BATU_BL_4M \| BATU_VS \
	267	\| BATU_VP)
	268	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	269	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	270
	271	/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
72cd4087	272	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE \| BATL_PP_RW \| \
8ed74341 HS	273	BATL_MEMCOHERENCE)
	274	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE \| BATU_BL_128M \| \
	275	BATU_VS \| BATU_VP)
72cd4087	276	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE \| BATL_PP_RW \| \
62ddcf05 HS	277	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	278	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	279
	280	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
72cd4087	281	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
62ddcf05 HS	282	BATL_MEMCOHERENCE)
	283	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \| BATU_BL_256M \| \
	284	BATU_VS \| BATU_VP)
72cd4087	285	#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
62ddcf05 HS	286	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	287	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	288
	289	/* Stack in dcache: cacheable, no memory coherence */
72cd4087	290	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
62ddcf05 HS	291	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| \
	292	BATU_VS \| BATU_VP)
	293	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	294	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	295
	296	/*
	297	* Internal Definitions
62ddcf05	298	*/
62ddcf05 HS	299	#define BOOTFLASH_START 0xF0000000
	300
	301	#define CONFIG_KM_CONSOLE_TTY "ttyS0"
	302
	303	/*
	304	* Environment Configuration
	305	*/
	306	#define CONFIG_ENV_OVERWRITE
	307	#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
	308	#define CONFIG_KM_DEF_ENV "km-common=empty\0"
	309	#endif
	310
b648bfc2 HB	311	#ifndef CONFIG_KM_DEF_ARCH
b648bfc2 HB	312	#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
62ddcf05 HS	313	#endif
	314
	315	#define CONFIG_EXTRA_ENV_SETTINGS \
	316	CONFIG_KM_DEF_ENV \
b648bfc2	317	CONFIG_KM_DEF_ARCH \
62ddcf05 HS	318	"EEprom_ivm=pca9547:70:9\0" \
	319	"newenv=" \
	320	"prot off 0xF00C0000 +0x40000 && " \
	321	"era 0xF00C0000 +0x40000\0" \
	322	"unlock=yes\0" \
	323	""
	324
	325	#if defined(CONFIG_UEC_ETH)
	326	#define CONFIG_HAS_ETH0
	327	#endif
	328
	329	#endif /* __CONFIG_KM83XX_H */