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877bfe37 VL |
1 | /* |
2 | * (C) Copyright 2013 Keymile AG | |
3 | * Valentin Longchamp <valentin.longchamp@keymile.com> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef _CONFIG_KMP204X_H | |
9 | #define _CONFIG_KMP204X_H | |
10 | ||
a5fbe742 | 11 | #define CONFIG_SYS_TEXT_BASE 0xfff40000 |
877bfe37 VL |
12 | |
13 | #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" | |
14 | ||
cf7707a1 VL |
15 | /* an additionnal option is required for UBI as subpage access is |
16 | * supported in u-boot */ | |
17 | #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" | |
18 | ||
877bfe37 VL |
19 | #define CONFIG_NAND_ECC_BCH |
20 | ||
21 | /* common KM defines */ | |
22 | #include "keymile-common.h" | |
23 | ||
24 | #define CONFIG_SYS_RAMBOOT | |
25 | #define CONFIG_RAMBOOT_PBL | |
26 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
27 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
e4536f8e MY |
28 | #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg |
29 | #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg | |
877bfe37 VL |
30 | |
31 | /* High Level Configuration Options */ | |
877bfe37 | 32 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
877bfe37 VL |
33 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
34 | #define CONFIG_MP /* support multiple processors */ | |
35 | ||
36 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
51370d56 | 37 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
b38eaec5 RD |
38 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
39 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
877bfe37 VL |
40 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
41 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
42 | ||
43 | #define CONFIG_SYS_DPAA_RMAN /* RMan */ | |
44 | ||
877bfe37 VL |
45 | /* Environment in SPI Flash */ |
46 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
877bfe37 VL |
47 | #define CONFIG_ENV_SPI_BUS 0 |
48 | #define CONFIG_ENV_SPI_CS 0 | |
49 | #define CONFIG_ENV_SPI_MAX_HZ 20000000 | |
50 | #define CONFIG_ENV_SPI_MODE 0 | |
51 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ | |
52 | #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ | |
53 | #define CONFIG_ENV_SECT_SIZE 0x010000 | |
54 | #define CONFIG_ENV_OFFSET_REDUND 0x110000 | |
55 | #define CONFIG_ENV_TOTAL_SIZE 0x020000 | |
56 | ||
57 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
58 | ||
59 | #ifndef __ASSEMBLY__ | |
60 | unsigned long get_board_sys_clk(unsigned long dummy); | |
61 | #endif | |
62 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
63 | ||
64 | /* | |
65 | * These can be toggled for performance analysis, otherwise use default. | |
66 | */ | |
67 | #define CONFIG_SYS_CACHE_STASHING | |
68 | #define CONFIG_BACKSIDE_L2_CACHE | |
69 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
70 | #define CONFIG_BTB /* toggle branch predition */ | |
71 | ||
72 | #define CONFIG_ENABLE_36BIT_PHYS | |
73 | ||
74 | #define CONFIG_ADDR_MAP | |
75 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
76 | ||
18794944 | 77 | #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ |
877bfe37 VL |
78 | |
79 | /* | |
80 | * Config the L3 Cache as L3 SRAM | |
81 | */ | |
82 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
83 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ | |
84 | CONFIG_RAMBOOT_TEXT_BASE) | |
85 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
86 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
87 | ||
88 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
89 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
90 | ||
91 | /* | |
92 | * DDR Setup | |
93 | */ | |
94 | #define CONFIG_VERY_BIG_RAM | |
95 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
96 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
97 | ||
98 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
99 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
100 | ||
101 | #define CONFIG_DDR_SPD | |
877bfe37 VL |
102 | #define CONFIG_FSL_DDR_INTERACTIVE |
103 | ||
104 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
105 | #define SPD_EEPROM_ADDRESS 0x54 | |
106 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
107 | ||
108 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
109 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
110 | ||
111 | /****************************************************************************** | |
112 | * (PRAM usage) | |
113 | * ... ------------------------------------------------------- | |
114 | * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM | |
115 | * ... |<------------------- pram -------------------------->| | |
116 | * ... ------------------------------------------------------- | |
117 | * @END_OF_RAM: | |
118 | * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose | |
119 | * @CONFIG_KM_PHRAM: address for /var | |
120 | * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) | |
121 | * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM | |
122 | */ | |
123 | ||
124 | /* size of rootfs in RAM */ | |
125 | #define CONFIG_KM_ROOTFSSIZE 0x0 | |
126 | /* pseudo-non volatile RAM [hex] */ | |
127 | #define CONFIG_KM_PNVRAM 0x80000 | |
128 | /* physical RAM MTD size [hex] */ | |
129 | #define CONFIG_KM_PHRAM 0x100000 | |
848b31ab VL |
130 | /* reserved pram area at the end of memory [hex] |
131 | * u-boot reserves some memory for the MP boot page */ | |
132 | #define CONFIG_KM_RESERVED_PRAM 0x1000 | |
133 | /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable | |
134 | * is not valid yet, which is the case for when u-boot copies itself to RAM */ | |
135 | #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) | |
877bfe37 VL |
136 | |
137 | #define CONFIG_KM_CRAMFS_ADDR 0x2000000 | |
138 | #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ | |
139 | #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ | |
140 | ||
877bfe37 VL |
141 | /* |
142 | * Local Bus Definitions | |
143 | */ | |
144 | ||
145 | /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ | |
146 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) | |
147 | ||
148 | /* Nand Flash */ | |
149 | #define CONFIG_NAND_FSL_ELBC | |
150 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
151 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
152 | ||
153 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
154 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
877bfe37 VL |
155 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
156 | ||
157 | #define CONFIG_BCH | |
158 | ||
159 | /* NAND flash config */ | |
160 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
161 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
162 | | BR_MS_FCM /* MSEL = FCM */ \ | |
163 | | BR_V) /* valid */ | |
164 | ||
165 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ | |
166 | | OR_FCM_BCTLD /* LBCTL not ass */ \ | |
167 | | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ | |
168 | | OR_FCM_RST /* 1 clk read setup */ \ | |
169 | | OR_FCM_PGS /* Large page size */ \ | |
170 | | OR_FCM_CST) /* 0.25 command setup */ | |
171 | ||
172 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
173 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
174 | ||
175 | /* QRIO FPGA */ | |
176 | #define CONFIG_SYS_QRIO_BASE 0xfb000000 | |
177 | #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull | |
178 | ||
179 | #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ | |
180 | | BR_PS_8 /* Port Size 8 bits */ \ | |
181 | | BR_DECC_OFF /* no error corr */ \ | |
182 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
183 | | BR_V) /* valid */ | |
184 | ||
185 | #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ | |
186 | | OR_GPCM_BCTLD /* no LCTL assert */ \ | |
187 | | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ | |
188 | | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ | |
189 | | OR_GPCM_TRLX /* relaxed tmgs */ \ | |
190 | | OR_GPCM_EAD) /* extra bus clk cycles */ | |
191 | ||
192 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ | |
193 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ | |
194 | ||
dd21f096 RB |
195 | /* bootcounter in QRIO */ |
196 | #define CONFIG_BOOTCOUNT_LIMIT | |
197 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) | |
198 | ||
877bfe37 | 199 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
f3e74d0a | 200 | #define CONFIG_MISC_INIT_F |
877bfe37 VL |
201 | #define CONFIG_MISC_INIT_R |
202 | #define CONFIG_LAST_STAGE_INIT | |
203 | ||
204 | #define CONFIG_HWCONFIG | |
205 | ||
206 | /* define to use L1 as initial stack */ | |
207 | #define CONFIG_L1_INIT_RAM | |
208 | #define CONFIG_SYS_INIT_RAM_LOCK | |
209 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
210 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
211 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
212 | /* The assembler doesn't like typecast */ | |
213 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
214 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
215 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
216 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
217 | ||
218 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
219 | GENERATED_GBL_DATA_SIZE) | |
220 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
221 | ||
222 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
a5fbe742 | 223 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
877bfe37 VL |
224 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
225 | ||
226 | /* Serial Port - controlled on board with jumper J8 | |
227 | * open - index 2 | |
228 | * shorted - index 1 | |
229 | */ | |
230 | #define CONFIG_CONS_INDEX 1 | |
877bfe37 VL |
231 | #define CONFIG_SYS_NS16550_SERIAL |
232 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
233 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
234 | ||
235 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
236 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
237 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
238 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
239 | ||
240 | #define CONFIG_KM_CONSOLE_TTY "ttyS0" | |
241 | ||
877bfe37 | 242 | /* I2C */ |
f3e74d0a | 243 | |
877bfe37 | 244 | #define CONFIG_SYS_I2C |
f3e74d0a RB |
245 | #define CONFIG_SYS_I2C_INIT_BOARD |
246 | #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ | |
877bfe37 VL |
247 | #define CONFIG_SYS_NUM_I2C_BUSES 3 |
248 | #define CONFIG_SYS_I2C_MAX_HOPS 1 | |
249 | #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ | |
250 | #define CONFIG_I2C_MULTI_BUS | |
251 | #define CONFIG_I2C_CMD_TREE | |
252 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
253 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
254 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
255 | #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ | |
256 | {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ | |
257 | {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ | |
258 | } | |
f3e74d0a RB |
259 | #ifndef __ASSEMBLY__ |
260 | void set_sda(int state); | |
261 | void set_scl(int state); | |
262 | int get_sda(void); | |
263 | int get_scl(void); | |
264 | #endif | |
877bfe37 VL |
265 | |
266 | #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ | |
267 | ||
268 | /* | |
269 | * eSPI - Enhanced SPI | |
270 | */ | |
877bfe37 | 271 | #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ |
877bfe37 VL |
272 | #define CONFIG_SF_DEFAULT_SPEED 20000000 |
273 | #define CONFIG_SF_DEFAULT_MODE 0 | |
274 | ||
275 | /* | |
276 | * General PCI | |
277 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
278 | */ | |
279 | ||
280 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
281 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
282 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
283 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
284 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
285 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
286 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
287 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
288 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
289 | ||
290 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
291 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 | |
292 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
293 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
294 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
295 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 | |
296 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
297 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull | |
298 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
299 | ||
300 | /* Qman/Bman */ | |
301 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
302 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 | |
303 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
304 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
305 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
306 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
307 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
308 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
309 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
310 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
311 | CONFIG_SYS_BMAN_CENA_SIZE) | |
312 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
313 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
877bfe37 VL |
314 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
315 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
316 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
317 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
318 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
319 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
320 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
321 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
322 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
323 | CONFIG_SYS_QMAN_CENA_SIZE) | |
324 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
325 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
877bfe37 VL |
326 | |
327 | #define CONFIG_SYS_DPAA_FMAN | |
328 | #define CONFIG_SYS_DPAA_PME | |
329 | /* Default address of microcode for the Linux Fman driver | |
330 | * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) | |
331 | * ucode is stored after env, so we got 0x120000. | |
332 | */ | |
333 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
dcf1d774 | 334 | #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 |
877bfe37 VL |
335 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
336 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
337 | ||
338 | #define CONFIG_FMAN_ENET | |
339 | #define CONFIG_PHYLIB_10G | |
340 | #define CONFIG_PHY_MARVELL /* there is a marvell phy */ | |
341 | ||
342 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
877bfe37 VL |
343 | |
344 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
877bfe37 VL |
345 | |
346 | /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ | |
347 | #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 | |
348 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
877bfe37 | 349 | #define CONFIG_ETHPRIME "FM1@DTSEC5" |
877bfe37 VL |
350 | |
351 | /* | |
352 | * Environment | |
353 | */ | |
354 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
355 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
356 | ||
88ac6ffa BR |
357 | /* |
358 | * Hardware Watchdog | |
359 | */ | |
360 | #define CONFIG_WATCHDOG /* enable CPU watchdog */ | |
361 | #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ | |
362 | #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ | |
363 | ||
364 | ||
877bfe37 VL |
365 | /* |
366 | * additionnal command line configuration. | |
367 | */ | |
368 | #define CONFIG_CMD_PCI | |
877bfe37 VL |
369 | |
370 | /* we don't need flash support */ | |
877bfe37 VL |
371 | #undef CONFIG_FLASH_CFI_MTD |
372 | #undef CONFIG_JFFS2_CMDLINE | |
373 | ||
374 | /* | |
375 | * For booting Linux, the board info and command line data | |
376 | * have to be in the first 64 MB of memory, since this is | |
377 | * the maximum mapped by the Linux kernel during initialization. | |
378 | */ | |
379 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ | |
380 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
381 | ||
382 | #ifdef CONFIG_CMD_KGDB | |
383 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
877bfe37 VL |
384 | #endif |
385 | ||
386 | #define __USB_PHY_TYPE utmi | |
eb364c3d | 387 | #define CONFIG_USB_EHCI_FSL |
877bfe37 VL |
388 | |
389 | /* | |
390 | * Environment Configuration | |
391 | */ | |
392 | #define CONFIG_ENV_OVERWRITE | |
393 | #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ | |
394 | #define CONFIG_KM_DEF_ENV "km-common=empty\0" | |
395 | #endif | |
396 | ||
397 | #ifndef MTDIDS_DEFAULT | |
398 | # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" | |
399 | #endif /* MTDIDS_DEFAULT */ | |
400 | ||
401 | #ifndef MTDPARTS_DEFAULT | |
402 | # define MTDPARTS_DEFAULT "mtdparts=" \ | |
403 | "fsl_elbc_nand:" \ | |
404 | "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" | |
405 | #endif /* MTDPARTS_DEFAULT */ | |
406 | ||
407 | /* architecture specific default bootargs */ | |
408 | #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" | |
409 | ||
410 | /* FIXME: FDT_ADDR is unspecified */ | |
411 | #define CONFIG_KM_DEF_ENV_CPU \ | |
412 | "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ | |
413 | "cramfsloadfdt=" \ | |
414 | "cramfsload ${fdt_addr_r} " \ | |
415 | "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ | |
416 | "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ | |
417 | "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ | |
418 | "update=" \ | |
419 | "sf probe 0;sf erase 0 +${filesize};" \ | |
420 | "sf write ${load_addr_r} 0 ${filesize};\0" \ | |
b1c2a7ae | 421 | "set_fdthigh=true\0" \ |
c6d32dfd | 422 | "checkfdt=true\0" \ |
877bfe37 VL |
423 | "" |
424 | ||
425 | #define CONFIG_HW_ENV_SETTINGS \ | |
426 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ | |
427 | "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ | |
428 | "usb_dr_mode=host\0" | |
429 | ||
430 | #define CONFIG_KM_NEW_ENV \ | |
431 | "newenv=sf probe 0;" \ | |
432 | "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ | |
433 | __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" | |
434 | ||
435 | /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ | |
436 | #ifndef CONFIG_KM_DEF_ARCH | |
437 | #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" | |
438 | #endif | |
439 | ||
440 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
441 | CONFIG_KM_DEF_ENV \ | |
442 | CONFIG_KM_DEF_ARCH \ | |
443 | CONFIG_KM_NEW_ENV \ | |
444 | CONFIG_HW_ENV_SETTINGS \ | |
445 | "EEprom_ivm=pca9547:70:9\0" \ | |
446 | "" | |
447 | ||
448 | #endif /* _CONFIG_KMP204X_H */ |