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de044361 HS |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
5 | * Copyright (C) 2007 Logic Product Development, Inc. | |
6 | * Peter Barada <peterb@logicpd.com> | |
7 | * | |
8 | * Copyright (C) 2007 MontaVista Software, Inc. | |
9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
10 | * | |
11 | * (C) Copyright 2008 | |
12 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
23 | /* | |
24 | * High Level Configuration Options | |
25 | */ | |
26 | #define CONFIG_E300 1 /* E300 family */ | |
27 | #define CONFIG_QE 1 /* Has QE */ | |
0f898604 | 28 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
de044361 HS |
29 | #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
30 | #define CONFIG_KMETER1 1 /* KMETER1 board specific */ | |
605f78e3 | 31 | #define CONFIG_HOSTNAME kmeter1 |
de044361 | 32 | |
1e8f4e78 HS |
33 | /* include common defines/options for all Keymile boards */ |
34 | #include "keymile-common.h" | |
35 | ||
19f0e930 | 36 | #define CONFIG_MISC_INIT_R 1 |
de044361 HS |
37 | /* |
38 | * System Clock Setup | |
39 | */ | |
40 | #define CONFIG_83XX_CLKIN 66000000 | |
41 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
42 | #define CONFIG_83XX_PCICLK 66000000 | |
43 | ||
44 | /* | |
45 | * Hardware Reset Configuration Word | |
46 | */ | |
47 | #define CONFIG_SYS_HRCW_LOW (\ | |
48 | HRCWL_CSB_TO_CLKIN_4X1 | \ | |
49 | HRCWL_CORE_TO_CSB_2X1 | \ | |
50 | HRCWL_CE_PLL_VCO_DIV_2 | \ | |
51 | HRCWL_CE_TO_PLL_1X6 ) | |
52 | ||
53 | #define CONFIG_SYS_HRCW_HIGH (\ | |
54 | HRCWH_CORE_ENABLE | \ | |
55 | HRCWH_FROM_0X00000100 | \ | |
605f78e3 | 56 | HRCWH_BOOTSEQ_DISABLE | \ |
de044361 HS |
57 | HRCWH_SW_WATCHDOG_DISABLE | \ |
58 | HRCWH_ROM_LOC_LOCAL_16BIT | \ | |
59 | HRCWH_BIG_ENDIAN | \ | |
605f78e3 | 60 | HRCWH_LALE_EARLY | \ |
de044361 HS |
61 | HRCWH_LDP_CLEAR ) |
62 | ||
63 | /* | |
64 | * System IO Config | |
65 | */ | |
66 | #define CONFIG_SYS_SICRH 0x00000006 | |
67 | #define CONFIG_SYS_SICRL 0x00000000 | |
68 | ||
de044361 HS |
69 | /* |
70 | * IMMR new address | |
71 | */ | |
72 | #define CONFIG_SYS_IMMR 0xE0000000 | |
73 | ||
74 | /* | |
75 | * DDR Setup | |
76 | */ | |
77 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ | |
78 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
79 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
80 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
81 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
82 | ||
83 | #define CFG_83XX_DDR_USES_CS0 | |
84 | ||
85 | #undef CONFIG_DDR_ECC | |
86 | ||
87 | /* | |
88 | * DDRCDR - DDR Control Driver Register | |
89 | */ | |
90 | ||
91 | #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ | |
92 | ||
93 | /* | |
94 | * Manually set up DDR parameters | |
95 | */ | |
96 | #define CONFIG_DDR_II | |
118cbe3c HS |
97 | #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ |
98 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f | |
de044361 HS |
99 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ |
100 | CSCONFIG_ROW_BIT_13 | \ | |
101 | CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) | |
102 | ||
103 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ | |
104 | SDRAM_CFG_SREN) | |
105 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
106 | #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
605f78e3 HS |
107 | #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ |
108 | (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT)) | |
de044361 | 109 | |
605f78e3 HS |
110 | #define CONFIG_SYS_DDRCDR 0x40000001 |
111 | #define CONFIG_SYS_DDR_MODE 0x47860452 | |
112 | #define CONFIG_SYS_DDR_MODE2 0x8080c000 | |
de044361 HS |
113 | |
114 | #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ | |
115 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ | |
116 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ | |
117 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ | |
118 | (0 << TIMING_CFG0_WWT_SHIFT) | \ | |
119 | (0 << TIMING_CFG0_RRT_SHIFT) | \ | |
120 | (0 << TIMING_CFG0_WRT_SHIFT) | \ | |
121 | (0 << TIMING_CFG0_RWT_SHIFT)) | |
122 | ||
605f78e3 | 123 | #define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \ |
de044361 | 124 | ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ |
605f78e3 HS |
125 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ |
126 | ( 3 << TIMING_CFG1_WRREC_SHIFT) | \ | |
127 | ( 7 << TIMING_CFG1_REFREC_SHIFT) | \ | |
128 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \ | |
129 | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ | |
130 | ( 3 << TIMING_CFG1_PRETOACT_SHIFT)) | |
131 | ||
132 | #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ | |
de044361 HS |
133 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ |
134 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ | |
605f78e3 HS |
135 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ |
136 | (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ | |
de044361 | 137 | (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ |
605f78e3 | 138 | (5 << TIMING_CFG2_CPO_SHIFT)) |
de044361 HS |
139 | |
140 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
141 | ||
de044361 HS |
142 | /* |
143 | * The reserved memory | |
144 | */ | |
145 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
146 | #define CONFIG_SYS_FLASH_BASE 0xF0000000 | |
147 | #define CONFIG_SYS_FLASH_BASE_1 0xF2000000 | |
605f78e3 HS |
148 | #define CONFIG_SYS_PIGGY_BASE 0xE8000000 |
149 | #define CONFIG_SYS_PIGGY_SIZE 128 | |
de044361 | 150 | #define CONFIG_SYS_PAXE_BASE 0xA0000000 |
605f78e3 | 151 | #define CONFIG_SYS_PAXE_SIZE 512 |
de044361 HS |
152 | |
153 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
154 | #define CONFIG_SYS_RAMBOOT | |
155 | #else | |
156 | #undef CONFIG_SYS_RAMBOOT | |
157 | #endif | |
158 | ||
4a9932a4 | 159 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
de044361 HS |
160 | |
161 | /* | |
162 | * Initial RAM Base Address Setup | |
163 | */ | |
164 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
165 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
166 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
167 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
168 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
169 | ||
170 | /* | |
171 | * Local Bus Configuration & Clock Setup | |
172 | */ | |
c7190f02 KP |
173 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
174 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 | |
175 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
de044361 HS |
176 | |
177 | /* | |
178 | * Init Local Bus Memory Controller: | |
179 | * | |
180 | * Bank Bus Machine PortSz Size Device | |
181 | * ---- --- ------- ------ ----- ------ | |
182 | * 0 Local GPCM 16 bit 256MB FLASH | |
605f78e3 HS |
183 | * 1 Local GPCM 8 bit 128MB GPIO/PIGGY |
184 | * 3 Local GPCM 8 bit 512MB PAXE | |
de044361 HS |
185 | * |
186 | */ | |
187 | /* | |
188 | * FLASH on the Local Bus | |
189 | */ | |
190 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ | |
191 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
192 | #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ | |
193 | #define CONFIG_SYS_FLASH_PROTECTION 1 | |
194 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
195 | ||
196 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ | |
197 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ | |
198 | ||
199 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
200 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | |
201 | BR_V) | |
202 | ||
203 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ | |
204 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ | |
205 | OR_GPCM_SCY_5 | \ | |
206 | OR_GPCM_TRLX | OR_GPCM_EAD) | |
207 | ||
208 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ | |
209 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
210 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 } | |
211 | ||
212 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
213 | ||
214 | /* | |
215 | * PRIO1/PIGGY on the local bus CS1 | |
216 | */ | |
217 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ | |
605f78e3 | 218 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ |
de044361 HS |
219 | |
220 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ | |
221 | (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ | |
222 | BR_V) | |
605f78e3 | 223 | #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \ |
de044361 HS |
224 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ |
225 | OR_GPCM_SCY_2 | \ | |
226 | OR_GPCM_TRLX | OR_GPCM_EAD) | |
227 | ||
228 | /* | |
229 | * PAXE on the local bus CS3 | |
230 | */ | |
231 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ | |
605f78e3 | 232 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ |
de044361 HS |
233 | |
234 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ | |
235 | (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ | |
236 | BR_V) | |
237 | #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ | |
238 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ | |
239 | OR_GPCM_SCY_2 | \ | |
240 | OR_GPCM_TRLX | OR_GPCM_EAD) | |
241 | ||
242 | /* | |
243 | * Serial Port | |
244 | */ | |
245 | #define CONFIG_CONS_INDEX 1 | |
246 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
247 | #define CONFIG_SYS_NS16550 | |
248 | #define CONFIG_SYS_NS16550_SERIAL | |
249 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
250 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
251 | ||
de044361 HS |
252 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
253 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
254 | ||
255 | /* Pass open firmware flat tree */ | |
256 | #define CONFIG_OF_LIBFDT 1 | |
257 | #define CONFIG_OF_BOARD_SETUP 1 | |
258 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
259 | ||
260 | /* | |
261 | * General PCI | |
262 | * Addresses are mapped 1-1. | |
263 | */ | |
264 | #undef CONFIG_PCI /* No PCI */ | |
265 | ||
266 | #ifndef CONFIG_NET_MULTI | |
267 | #define CONFIG_NET_MULTI 1 | |
268 | #endif | |
de044361 HS |
269 | /* |
270 | * QE UEC ethernet configuration | |
271 | */ | |
272 | #define CONFIG_UEC_ETH | |
273 | #define CONFIG_ETHPRIME "FSL UEC0" | |
274 | ||
275 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
276 | #define UEC_VERBOSE_DEBUG 1 | |
277 | ||
278 | #ifdef CONFIG_UEC_ETH1 | |
279 | #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ | |
280 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ | |
281 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 | |
282 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
283 | #define CONFIG_SYS_UEC1_PHY_ADDR 0 | |
284 | #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII | |
285 | #endif | |
286 | ||
287 | /* | |
288 | * Environment | |
289 | */ | |
290 | ||
291 | #ifndef CONFIG_SYS_RAMBOOT | |
292 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
293 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
294 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
de044361 HS |
295 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) |
296 | ||
297 | /* Address and size of Redundant Environment Sector */ | |
298 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) | |
299 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
300 | ||
301 | #else /* CFG_RAMBOOT */ | |
302 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ | |
303 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
605f78e3 | 304 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
de044361 HS |
305 | #define CONFIG_ENV_SIZE 0x2000 |
306 | #endif /* CFG_RAMBOOT */ | |
307 | ||
19f0e930 HS |
308 | /* I2C */ |
309 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
310 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
311 | #define CONFIG_FSL_I2C | |
312 | #define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ | |
313 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
314 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
315 | #define CONFIG_I2C_MULTI_BUS 1 | |
19f0e930 HS |
316 | #define CONFIG_I2C_MUX 1 |
317 | ||
318 | /* EEprom support */ | |
319 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
19f0e930 HS |
320 | |
321 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ | |
322 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
323 | #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ | |
324 | #define CONFIG_SYS_DTT_MAX_TEMP 70 | |
325 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
326 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
dc71b248 | 327 | #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) |
19f0e930 | 328 | |
de425092 HS |
329 | #if defined(CONFIG_CMD_NAND) |
330 | #define CONFIG_NAND_KMETER1 | |
331 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
332 | #define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE | |
333 | #endif | |
334 | ||
de044361 HS |
335 | #if defined(CONFIG_PCI) |
336 | #define CONFIG_CMD_PCI | |
337 | #endif | |
338 | ||
339 | #if defined(CFG_RAMBOOT) | |
bdab39d3 | 340 | #undef CONFIG_CMD_SAVEENV |
de044361 HS |
341 | #undef CONFIG_CMD_LOADS |
342 | #endif | |
343 | ||
de044361 HS |
344 | /* |
345 | * For booting Linux, the board info and command line data | |
346 | * have to be in the first 8 MB of memory, since this is | |
347 | * the maximum mapped by the Linux kernel during initialization. | |
348 | */ | |
349 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
350 | ||
351 | /* | |
352 | * Core HID Setup | |
353 | */ | |
354 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
355 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
356 | #define CONFIG_SYS_HID2 HID2_HBE | |
357 | ||
358 | /* | |
359 | * MMU Setup | |
360 | */ | |
361 | ||
362 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
363 | ||
364 | /* DDR: cache cacheable */ | |
365 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ | |
366 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
367 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
368 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
369 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
370 | ||
371 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
372 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ | |
373 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
374 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) | |
375 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
376 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
377 | ||
378 | /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ | |
379 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
605f78e3 | 380 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP) |
de044361 HS |
381 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ |
382 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
383 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
384 | ||
385 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
386 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
387 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
388 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ | |
389 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
390 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
391 | ||
392 | /* Stack in dcache: cacheable, no memory coherence */ | |
393 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) | |
394 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
395 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
396 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
397 | ||
398 | /* PAXE: icache cacheable, but dcache-inhibit and guarded */ | |
399 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
605f78e3 | 400 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
de044361 HS |
401 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ |
402 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
403 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
404 | ||
405 | #ifdef CONFIG_PCI | |
406 | /* PCI MEM space: cacheable */ | |
407 | #define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) | |
408 | #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
409 | #define CFG_DBAT6L CFG_IBAT6L | |
410 | #define CFG_DBAT6U CFG_IBAT6U | |
411 | /* PCI MMIO space: cache-inhibit and guarded */ | |
412 | #define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ | |
413 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
414 | #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
415 | #define CFG_DBAT7L CFG_IBAT7L | |
416 | #define CFG_DBAT7U CFG_IBAT7U | |
417 | #else /* CONFIG_PCI */ | |
418 | #define CONFIG_SYS_IBAT6L (0) | |
419 | #define CONFIG_SYS_IBAT6U (0) | |
420 | #define CONFIG_SYS_IBAT7L (0) | |
421 | #define CONFIG_SYS_IBAT7U (0) | |
422 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
423 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
424 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
425 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
426 | #endif /* CONFIG_PCI */ | |
427 | ||
428 | /* | |
429 | * Internal Definitions | |
430 | * | |
431 | * Boot Flags | |
432 | */ | |
433 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
434 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
435 | ||
605f78e3 HS |
436 | #define BOOTFLASH_START F0000000 |
437 | ||
438 | #define CONFIG_PRAM 512 /* protected RAM [KBytes] */ | |
439 | ||
dc71b248 | 440 | #define MTDIDS_DEFAULT "nor2=app" |
605f78e3 HS |
441 | #define MTDPARTS_DEFAULT \ |
442 | "mtdparts=app:256k(u-boot),128k(env),128k(envred)," \ | |
443 | "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)" | |
444 | ||
de044361 HS |
445 | /* |
446 | * Environment Configuration | |
447 | */ | |
448 | #define CONFIG_ENV_OVERWRITE | |
605f78e3 HS |
449 | #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ |
450 | #define CONFIG_KM_DEF_ENV "km-common=empty\0" | |
de044361 HS |
451 | #endif |
452 | ||
de044361 | 453 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
605f78e3 | 454 | CONFIG_KM_DEF_ENV \ |
de044361 | 455 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
364123db | 456 | "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ |
de044361 | 457 | "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ |
de044361 HS |
458 | "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ |
459 | "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ | |
364123db | 460 | "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0" \ |
de044361 | 461 | "unlock=yes\0" \ |
364123db HS |
462 | "fdt_addr=F0080000\0" \ |
463 | "kernel_addr=F00a0000\0" \ | |
464 | "ramdisk_addr=F03a0000\0" \ | |
465 | "ramdisk_addr_r=F10000\0" \ | |
19f0e930 HS |
466 | "EEprom_ivm=pca9547:70:9\0" \ |
467 | "dtt_bus=pca9547:70:a\0" \ | |
605f78e3 HS |
468 | "mtdids=nor0=app \0" \ |
469 | "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ | |
de044361 HS |
470 | "" |
471 | ||
605f78e3 HS |
472 | #if defined(CONFIG_UEC_ETH) |
473 | #define CONFIG_HAS_ETH0 | |
474 | #endif | |
475 | ||
de044361 | 476 | #endif /* __CONFIG_H */ |