projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 87dc0968 | 1 | /* |
| a87fb1b3 | 2 | * (C) Copyright 2007-2009 |
| 87dc0968 LJ |
3 | * Larry Johnson, lrj@acm.org |
| 4 | * | |
| 5 | * (C) Copyright 2006-2007 | |
| 6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 7 | * | |
| 8 | * (C) Copyright 2006 | |
| 9 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
| 10 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or | |
| 13 | * modify it under the terms of the GNU General Public License as | |
| 14 | * published by the Free Software Foundation; either version 2 of | |
| 15 | * the License, or (at your option) any later version. | |
| 16 | * | |
| 17 | * This program is distributed in the hope that it will be useful, | |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 20 | * GNU General Public License for more details. | |
| 21 | * | |
| 22 | * You should have received a copy of the GNU General Public License | |
| 23 | * along with this program; if not, write to the Free Software | |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 25 | * MA 02111-1307 USA | |
| 26 | */ | |
| 27 | ||
| 214398d9 | 28 | /* |
| 87dc0968 | 29 | * korat.h - configuration for Korat board |
| 214398d9 | 30 | */ |
| 87dc0968 LJ |
31 | #ifndef __CONFIG_H |
| 32 | #define __CONFIG_H | |
| 33 | ||
| 214398d9 | 34 | /* |
| 87dc0968 | 35 | * High Level Configuration Options |
| 214398d9 LJ |
36 | */ |
| 37 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
| 38 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
| 87dc0968 LJ |
39 | #define CONFIG_SYS_CLK_FREQ 33333333 |
| 40 | ||
| 214398d9 LJ |
41 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 42 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
| 87dc0968 | 43 | |
| 214398d9 | 44 | /* |
| 87dc0968 | 45 | * Manufacturer's information serial EEPROM parameters |
| 214398d9 LJ |
46 | */ |
| 47 | #define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */ | |
| 6433fa20 LJ |
48 | #define MAN_INFO_FIELD 2 |
| 49 | #define MAN_INFO_LENGTH 9 | |
| 87dc0968 | 50 | #define MAN_MAC_ADDR_FIELD 3 |
| 6433fa20 | 51 | #define MAN_MAC_ADDR_LENGTH 12 |
| 87dc0968 | 52 | |
| 214398d9 LJ |
53 | /* |
| 54 | * Base addresses -- Note these are effective addresses where the actual | |
| 55 | * resources get mapped (not physical addresses). | |
| 56 | */ | |
| 6d0f6bcf JCPV |
57 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */ |
| 58 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */ | |
| 59 | ||
| 60 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
| 61 | #define CONFIG_SYS_FLASH0_SIZE 0x01000000 | |
| 62 | #define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE) | |
| 63 | #define CONFIG_SYS_FLASH1_TOP 0xF8000000 | |
| 64 | #define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000 | |
| 65 | #define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE) | |
| 66 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */ | |
| 67 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
| 68 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ | |
| 69 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE | |
| 70 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
| 71 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
| 87dc0968 LJ |
72 | |
| 73 | /* Don't change either of these */ | |
| 6d0f6bcf | 74 | #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ |
| 87dc0968 | 75 | |
| 6d0f6bcf JCPV |
76 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
| 77 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
| 78 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
| 79 | #define CONFIG_SYS_CPLD_BASE 0xc0000000 | |
| 87dc0968 | 80 | |
| 214398d9 | 81 | /* |
| 87dc0968 | 82 | * Initial RAM & stack pointer |
| 214398d9 | 83 | */ |
| 87dc0968 | 84 | /* 440EPx has 16KB of internal SRAM, so no need for D-Cache */ |
| 6d0f6bcf JCPV |
85 | #undef CONFIG_SYS_INIT_RAM_DCACHE |
| 86 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ | |
| 87 | #define CONFIG_SYS_INIT_RAM_END (4 << 10) | |
| 88 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
| 89 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 90 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR | |
| 87dc0968 | 91 | |
| 214398d9 | 92 | /* |
| 87dc0968 | 93 | * Serial Port |
| 214398d9 | 94 | */ |
| 6d0f6bcf | 95 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
| 87dc0968 LJ |
96 | #define CONFIG_BAUDRATE 115200 |
| 97 | #define CONFIG_SERIAL_MULTI 1 | |
| 98 | /* define this if you want console on UART1 */ | |
| 99 | #undef CONFIG_UART1_CONSOLE | |
| 100 | ||
| 6d0f6bcf | 101 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 87dc0968 LJ |
102 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 103 | ||
| 214398d9 | 104 | /* |
| 87dc0968 | 105 | * Environment |
| 214398d9 | 106 | */ |
| 5a1aceb0 | 107 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */ |
| 87dc0968 | 108 | |
| 214398d9 | 109 | /* |
| 87dc0968 | 110 | * FLASH related |
| 214398d9 | 111 | */ |
| 6d0f6bcf | 112 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| 00b1883a | 113 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 6433fa20 | 114 | #define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */ |
| 87dc0968 | 115 | |
| 6d0f6bcf | 116 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR } |
| 87dc0968 | 117 | |
| 6d0f6bcf JCPV |
118 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 119 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */ | |
| 87dc0968 | 120 | |
| 6d0f6bcf JCPV |
121 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 122 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 87dc0968 | 123 | |
| 6d0f6bcf JCPV |
124 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| 125 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
| 87dc0968 | 126 | |
| 6d0f6bcf JCPV |
127 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 128 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
| 87dc0968 | 129 | |
| 0e8d1586 | 130 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
| 6d0f6bcf | 131 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE) |
| 0e8d1586 | 132 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
| 87dc0968 | 133 | |
| 6433fa20 | 134 | /* Address and size of Redundant Environment Sector */ |
| 0e8d1586 JCPV |
135 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) |
| 136 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| 87dc0968 | 137 | |
| 214398d9 | 138 | /* |
| 87dc0968 | 139 | * DDR SDRAM |
| 214398d9 | 140 | */ |
| 214398d9 LJ |
141 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ |
| 142 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
| 143 | #define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ | |
| 144 | #define CONFIG_DDR_ECC /* Use ECC when available */ | |
| 87dc0968 LJ |
145 | #define SPD_EEPROM_ADDRESS {0x50} |
| 146 | #define CONFIG_PROG_SDRAM_TLB | |
| a87fb1b3 LJ |
147 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */ |
| 148 | /* per 440EPx Errata CHIP_11 */ | |
| 87dc0968 | 149 | |
| 214398d9 | 150 | /* |
| 87dc0968 | 151 | * I2C |
| 214398d9 LJ |
152 | */ |
| 153 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
| 154 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 6d0f6bcf JCPV |
155 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 156 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 87dc0968 | 157 | |
| 6d0f6bcf JCPV |
158 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
| 159 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
| 160 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 161 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 162 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 87dc0968 LJ |
163 | |
| 164 | /* I2C RTC */ | |
| 165 | #define CONFIG_RTC_M41T60 1 | |
| 6d0f6bcf | 166 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 87dc0968 LJ |
167 | |
| 168 | /* I2C SYSMON (LM73) */ | |
| 214398d9 LJ |
169 | #define CONFIG_DTT_LM73 1 /* National Semi's LM73 */ |
| 170 | #define CONFIG_DTT_SENSORS {2} /* Sensor addresses */ | |
| 6d0f6bcf JCPV |
171 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
| 172 | #define CONFIG_SYS_DTT_MIN_TEMP -30 | |
| 87dc0968 LJ |
173 | |
| 174 | #define CONFIG_PREBOOT "echo;" \ | |
| a87fb1b3 | 175 | "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \ |
| 87dc0968 LJ |
176 | "echo" |
| 177 | ||
| 178 | #undef CONFIG_BOOTARGS | |
| 179 | ||
| 180 | /* Setup some board specific values for the default environment variables */ | |
| 181 | #define CONFIG_HOSTNAME korat | |
| 87dc0968 | 182 | |
| 6433fa20 | 183 | /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */ |
| 47ce4a28 | 184 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| a87fb1b3 LJ |
185 | "u_boot=korat/u-boot.bin\0" \ |
| 186 | "load=tftp 200000 ${u_boot}\0" \ | |
| 187 | "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \ | |
| 188 | "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \ | |
| 189 | "F7F60000 F7FBFFFF\0" \ | |
| 190 | "upd=run load update\0" \ | |
| 191 | "bootfile=korat/uImage\0" \ | |
| 192 | "dtb=korat/korat.dtb\0" \ | |
| 193 | "kernel_addr=F4000000\0" \ | |
| 194 | "ramdisk_addr=F4400000\0" \ | |
| 195 | "dtb_addr=F41E0000\0" \ | |
| 196 | "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \ | |
| 197 | "cp.b ${fileaddr} F4000000 ${filesize}\0" \ | |
| 198 | "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \ | |
| 199 | "cp.b ${fileaddr} F41E0000 ${filesize}\0" \ | |
| 200 | "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \ | |
| 201 | "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \ | |
| 202 | "${dtb}\0" \ | |
| 203 | "rd_size=73728\0" \ | |
| 204 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
| 205 | "ramdisk_size=${rd_size}\0" \ | |
| 206 | "usbdev=sda1\0" \ | |
| 207 | "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \ | |
| 208 | "rootpath=/opt/eldk/ppc_4xxFP\0" \ | |
| 87dc0968 LJ |
209 | "netdev=eth0\0" \ |
| 210 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 211 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| a87fb1b3 LJ |
212 | "pciclk=33\0" \ |
| 213 | "addide=setenv bootargs ${bootargs} ide=reverse " \ | |
| 214 | "idebus=${pciclk}\0" \ | |
| 87dc0968 LJ |
215 | "addip=setenv bootargs ${bootargs} " \ |
| 216 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 217 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 218 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| a87fb1b3 LJ |
219 | "flash_cf=run usbargs addide addip addtty; " \ |
| 220 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
| 221 | "flash_nfs=run nfsargs addide addip addtty; " \ | |
| 222 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
| 223 | "flash_self=run ramargs addip addtty; " \ | |
| 224 | "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \ | |
| 87dc0968 | 225 | "" |
| a87fb1b3 LJ |
226 | |
| 227 | #define CONFIG_BOOTCOMMAND "run flash_cf" | |
| 87dc0968 | 228 | |
| 214398d9 | 229 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 87dc0968 | 230 | |
| 214398d9 | 231 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 6d0f6bcf | 232 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 87dc0968 | 233 | |
| 96e21f86 | 234 | #define CONFIG_PPC4xx_EMAC |
| 47ce4a28 | 235 | #define CONFIG_IBM_EMAC4_V4 1 |
| 214398d9 LJ |
236 | #define CONFIG_MII 1 /* MII PHY management */ |
| 237 | #define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ | |
| 87dc0968 LJ |
238 | #define CONFIG_PHY_DYNAMIC_ANEG 1 |
| 239 | ||
| 6433fa20 | 240 | #undef CONFIG_PHY_RESET /* Don't do software PHY reset */ |
| 87dc0968 LJ |
241 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 242 | ||
| 243 | #define CONFIG_HAS_ETH0 | |
| 6d0f6bcf | 244 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */ |
| 214398d9 | 245 | /* buffers & descriptors */ |
| 87dc0968 | 246 | #define CONFIG_NET_MULTI 1 |
| 214398d9 | 247 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 87dc0968 LJ |
248 | #define CONFIG_PHY1_ADDR 3 |
| 249 | ||
| 250 | /* USB */ | |
| 251 | #define CONFIG_USB_OHCI | |
| 252 | #define CONFIG_USB_STORAGE | |
| 253 | ||
| 254 | /* Comment this out to enable USB 1.1 device */ | |
| 255 | #define USB_2_0_DEVICE | |
| 256 | ||
| 257 | /* Partitions */ | |
| 258 | #define CONFIG_MAC_PARTITION | |
| 259 | #define CONFIG_DOS_PARTITION | |
| 260 | #define CONFIG_ISO_PARTITION | |
| 261 | ||
| 262 | /* | |
| 263 | * BOOTP options | |
| 264 | */ | |
| 265 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 266 | #define CONFIG_BOOTP_BOOTPATH | |
| 267 | #define CONFIG_BOOTP_GATEWAY | |
| 268 | #define CONFIG_BOOTP_HOSTNAME | |
| 269 | #define CONFIG_BOOTP_SUBNETMASK | |
| 270 | ||
| 271 | /* | |
| 272 | * Command line configuration. | |
| 273 | */ | |
| 274 | #include <config_cmd_default.h> | |
| 275 | ||
| 276 | #define CONFIG_CMD_ASKENV | |
| 277 | #define CONFIG_CMD_DATE | |
| 278 | #define CONFIG_CMD_DHCP | |
| 279 | #define CONFIG_CMD_DTT | |
| 280 | #define CONFIG_CMD_DIAG | |
| 281 | #define CONFIG_CMD_EEPROM | |
| 282 | #define CONFIG_CMD_ELF | |
| 283 | #define CONFIG_CMD_FAT | |
| 284 | #define CONFIG_CMD_I2C | |
| 87dc0968 LJ |
285 | #define CONFIG_CMD_IRQ |
| 286 | #define CONFIG_CMD_MII | |
| 287 | #define CONFIG_CMD_NET | |
| 288 | #define CONFIG_CMD_NFS | |
| 289 | #define CONFIG_CMD_PCI | |
| 290 | #define CONFIG_CMD_PING | |
| 291 | #define CONFIG_CMD_REGINFO | |
| 292 | #define CONFIG_CMD_SDRAM | |
| 293 | #define CONFIG_CMD_USB | |
| 294 | ||
| 295 | /* POST support */ | |
| a87fb1b3 LJ |
296 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
| 297 | CONFIG_SYS_POST_CPU | \ | |
| 298 | CONFIG_SYS_POST_ECC | \ | |
| 299 | CONFIG_SYS_POST_ETHER | \ | |
| 300 | CONFIG_SYS_POST_FPU | \ | |
| 301 | CONFIG_SYS_POST_I2C | \ | |
| 302 | CONFIG_SYS_POST_MEMORY | \ | |
| 303 | CONFIG_SYS_POST_RTC | \ | |
| 304 | CONFIG_SYS_POST_SPR | \ | |
| 6d0f6bcf JCPV |
305 | CONFIG_SYS_POST_UART) |
| 306 | ||
| 307 | #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) | |
| 87dc0968 | 308 | #define CONFIG_LOGBUFFER |
| 6d0f6bcf | 309 | #define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */ |
| 87dc0968 | 310 | |
| 6d0f6bcf | 311 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
| 87dc0968 LJ |
312 | |
| 313 | #define CONFIG_SUPPORT_VFAT | |
| 314 | ||
| 214398d9 | 315 | /* |
| 87dc0968 | 316 | * Miscellaneous configurable options |
| 214398d9 | 317 | */ |
| 6d0f6bcf JCPV |
318 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 319 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 87dc0968 | 320 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 321 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 87dc0968 | 322 | #else |
| 6d0f6bcf | 323 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 87dc0968 | 324 | #endif |
| 6d0f6bcf | 325 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 53677ef1 | 326 | /* Print Buffer Size */ |
| 6d0f6bcf JCPV |
327 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 328 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 87dc0968 | 329 | |
| 6d0f6bcf JCPV |
330 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 331 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 87dc0968 | 332 | |
| 6d0f6bcf JCPV |
333 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 334 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
| 87dc0968 | 335 | |
| 6d0f6bcf | 336 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 87dc0968 | 337 | |
| 214398d9 LJ |
338 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 339 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
| 340 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
| 341 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
| 342 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
| 87dc0968 | 343 | |
| 6433fa20 LJ |
344 | /* |
| 345 | * Korat-specific options | |
| 346 | */ | |
| 6d0f6bcf | 347 | #define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */ |
| 6433fa20 | 348 | |
| 214398d9 | 349 | /* |
| 87dc0968 | 350 | * PCI stuff |
| 214398d9 | 351 | */ |
| 87dc0968 | 352 | /* General PCI */ |
| 214398d9 LJ |
353 | #define CONFIG_PCI /* include pci support */ |
| 354 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 6d0f6bcf | 355 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ |
| 214398d9 | 356 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 6d0f6bcf JCPV |
357 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ |
| 358 | /* CONFIG_SYS_PCI_MEMBASE */ | |
| 87dc0968 | 359 | /* Board-specific PCI */ |
| 6d0f6bcf JCPV |
360 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 361 | #define CONFIG_SYS_PCI_MASTER_INIT | |
| 87dc0968 | 362 | |
| 6d0f6bcf JCPV |
363 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 364 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
| 87dc0968 LJ |
365 | |
| 366 | /* | |
| 214398d9 LJ |
367 | * For booting Linux, the board info and command line data have to be in the |
| 368 | * first 8 MB of memory, since this is the maximum mapped by the Linux kernel | |
| 369 | * during initialization. | |
| 87dc0968 | 370 | */ |
| 6d0f6bcf | 371 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 87dc0968 | 372 | |
| 214398d9 | 373 | /* |
| 87dc0968 | 374 | * External Bus Controller (EBC) Setup |
| 214398d9 | 375 | */ |
| 87dc0968 LJ |
376 | |
| 377 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
| 6d0f6bcf JCPV |
378 | #if CONFIG_SYS_FLASH0_SIZE == 0x01000000 |
| 379 | #define CONFIG_SYS_EBC_PB0AP 0x04017300 | |
| 380 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000) | |
| 381 | #elif CONFIG_SYS_FLASH0_SIZE == 0x04000000 | |
| 382 | #define CONFIG_SYS_EBC_PB0AP 0x04017300 | |
| 383 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000) | |
| 6433fa20 | 384 | #else |
| 6d0f6bcf | 385 | #error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE |
| 6433fa20 | 386 | #endif |
| 87dc0968 LJ |
387 | |
| 388 | /* Memory Bank 1 (NOR-FLASH) initialization */ | |
| 6d0f6bcf JCPV |
389 | #if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000 |
| 390 | #define CONFIG_SYS_EBC_PB1AP 0x04017300 | |
| 391 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000) | |
| 6433fa20 | 392 | #else |
| 6d0f6bcf | 393 | #error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE |
| 6433fa20 | 394 | #endif |
| 87dc0968 LJ |
395 | |
| 396 | /* Memory Bank 2 (CPLD) initialization */ | |
| 6d0f6bcf JCPV |
397 | #define CONFIG_SYS_EBC_PB2AP 0x04017300 |
| 398 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000) | |
| 87dc0968 | 399 | |
| 214398d9 | 400 | /* |
| 0ddd969a LJ |
401 | * GPIO Setup |
| 402 | * | |
| 403 | * Korat GPIO usage: | |
| 404 | * | |
| 405 | * Init. | |
| 406 | * Pin Source I/O value Function | |
| 407 | * ------ ------ --- ----- --------------------------------- | |
| 408 | * GPIO00 Alt1 I/O x PerAddr07 | |
| 409 | * GPIO01 Alt1 I/O x PerAddr06 | |
| 410 | * GPIO02 Alt1 I/O x PerAddr05 | |
| 411 | * GPIO03 GPIO x x GPIO03 to expansion bus connector | |
| 412 | * GPIO04 GPIO x x GPIO04 to expansion bus connector | |
| 413 | * GPIO05 GPIO x x GPIO05 to expansion bus connector | |
| 414 | * GPIO06 Alt1 O x PerCS1 (2nd NOR flash) | |
| 415 | * GPIO07 Alt1 O x PerCS2 (CPLD) | |
| 416 | * GPIO08 Alt1 O x PerCS3 to expansion bus connector | |
| 417 | * GPIO09 Alt1 O x PerCS4 to expansion bus connector | |
| 418 | * GPIO10 Alt1 O x PerCS5 to expansion bus connector | |
| 419 | * GPIO11 Alt1 I x PerErr | |
| 420 | * GPIO12 GPIO O 0 ATMega !Reset | |
| a87fb1b3 | 421 | * GPIO13 GPIO x x Test Point 2 (TP2) |
| 0ddd969a LJ |
422 | * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8) |
| 423 | * GPIO15 GPIO O 0 CPU Run LED !On | |
| 424 | * GPIO16 Alt1 O x GMC1TxD0 | |
| 425 | * GPIO17 Alt1 O x GMC1TxD1 | |
| 426 | * GPIO18 Alt1 O x GMC1TxD2 | |
| 427 | * GPIO19 Alt1 O x GMC1TxD3 | |
| 428 | * GPIO20 Alt1 I x RejectPkt0 | |
| 429 | * GPIO21 Alt1 I x RejectPkt1 | |
| 430 | * GPIO22 GPIO I x PGOOD_DDR | |
| 431 | * GPIO23 Alt1 O x SCPD0 | |
| 432 | * GPIO24 Alt1 O x GMC0TxD2 | |
| 433 | * GPIO25 Alt1 O x GMC0TxD3 | |
| 434 | * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4) | |
| 435 | * GPIO27 GPIO O 0 PHY #0 1000BASE-X select | |
| 436 | * GPIO28 GPIO O 0 PHY #1 1000BASE-X select | |
| 437 | * GPIO29 GPIO I x Test jumper !Present | |
| 438 | * GPIO30 GPIO I x SFP module #0 !Present | |
| 439 | * GPIO31 GPIO I x SFP module #1 !Present | |
| 440 | * | |
| 441 | * GPIO32 GPIO O 1 SFP module #0 Tx !Enable | |
| 442 | * GPIO33 GPIO O 1 SFP module #1 Tx !Enable | |
| 443 | * GPIO34 Alt2 I x !UART1_CTS | |
| 444 | * GPIO35 Alt2 O x !UART1_RTS | |
| 445 | * GPIO36 Alt1 I x !UART0_CTS | |
| 446 | * GPIO37 Alt1 O x !UART0_RTS | |
| 447 | * GPIO38 Alt2 O x UART1_Tx | |
| 448 | * GPIO39 Alt2 I x UART1_Rx | |
| 449 | * GPIO40 Alt1 I x IRQ0 (Ethernet 0) | |
| 450 | * GPIO41 Alt1 I x IRQ1 (Ethernet 1) | |
| 451 | * GPIO42 Alt1 I x IRQ2 (PCI interrupt) | |
| 452 | * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD) | |
| 453 | * GPIO44 xxxx x x (grounded through pulldown) | |
| 454 | * GPIO45 GPIO O 0 PHY #0 Enable | |
| 455 | * GPIO46 GPIO O 0 PHY #1 Enable | |
| 456 | * GPIO47 GPIO I x Reset switch !Pressed | |
| 457 | * GPIO48 GPIO I x Shutdown switch !Pressed | |
| 458 | * GPIO49 xxxx x x (reserved for trace port) | |
| 459 | * . . . . . | |
| 460 | * . . . . . | |
| 461 | * . . . . . | |
| 462 | * GPIO63 xxxx x x (reserved for trace port) | |
| 214398d9 | 463 | */ |
| 0ddd969a | 464 | |
| 6d0f6bcf JCPV |
465 | #define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12 |
| 466 | #define CONFIG_SYS_GPIO_ATMEGA_SS_ 13 | |
| 467 | #define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27 | |
| 468 | #define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28 | |
| 469 | #define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30 | |
| 470 | #define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31 | |
| 471 | #define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32 | |
| 472 | #define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33 | |
| 473 | #define CONFIG_SYS_GPIO_PHY0_EN 45 | |
| 474 | #define CONFIG_SYS_GPIO_PHY1_EN 46 | |
| 475 | #define CONFIG_SYS_GPIO_RESET_PRESSED_ 47 | |
| 0ddd969a | 476 | |
| 214398d9 | 477 | /* |
| 0ddd969a LJ |
478 | * PPC440 GPIO Configuration |
| 479 | */ | |
| 6d0f6bcf | 480 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
| 0ddd969a LJ |
481 | { \ |
| 482 | /* GPIO Core 0 */ \ | |
| 483 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
| 484 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
| 485 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
| 486 | {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
| 487 | {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
| 488 | {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
| 489 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
| 490 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
| 491 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
| 492 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
| 493 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
| 494 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
| 495 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
| a87fb1b3 | 496 | {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ |
| 0ddd969a LJ |
497 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ |
| 498 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ | |
| 499 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ | |
| 500 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \ | |
| 501 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \ | |
| 502 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \ | |
| 503 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
| 504 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
| 505 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
| 506 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
| 507 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \ | |
| 508 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \ | |
| 509 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
| 510 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
| 511 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ | |
| 512 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
| 513 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
| 514 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
| 515 | }, \ | |
| 516 | { \ | |
| 517 | /* GPIO Core 1 */ \ | |
| 518 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
| 519 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
| 520 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
| 521 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
| 522 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
| 523 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
| 524 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
| 525 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
| 526 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ | |
| 527 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
| 528 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
| 529 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
| 530 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
| 531 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
| 532 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
| 533 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
| 534 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
| 535 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
| 536 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ | |
| 537 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ | |
| 538 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
| 539 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
| 540 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
| 541 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
| 542 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
| 543 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
| 544 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
| 545 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
| 546 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
| 547 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
| 548 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
| 549 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
| 550 | } \ | |
| 551 | } | |
| 552 | ||
| 87dc0968 LJ |
553 | /* |
| 554 | * Internal Definitions | |
| 555 | * | |
| 556 | * Boot Flags | |
| 557 | */ | |
| 214398d9 LJ |
558 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 559 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 87dc0968 LJ |
560 | |
| 561 | #if defined(CONFIG_CMD_KGDB) | |
| 214398d9 LJ |
562 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 563 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 87dc0968 | 564 | #endif |
| 214398d9 | 565 | |
| 47ce4a28 LJ |
566 | /* Pass open firmware flat tree */ |
| 567 | #define CONFIG_OF_LIBFDT 1 | |
| 568 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 569 | ||
| 87dc0968 | 570 | #endif /* __CONFIG_H */ |