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[people/ms/u-boot.git] / include / configs / korat.h
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87dc0968 1/*
a87fb1b3 2 * (C) Copyright 2007-2009
87dc0968
LJ		 3 * Larry Johnson, lrj@acm.org
4 *
5 * (C) Copyright 2006-2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * (C) Copyright 2006
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
214398d9 28/*
87dc0968 29 * korat.h - configuration for Korat board
214398d9 30 */
87dc0968
LJ		 31#ifndef __CONFIG_H
32#define __CONFIG_H
33
214398d9 34/*
87dc0968 35 * High Level Configuration Options
214398d9
LJ		 36 */
37#define CONFIG_440EPX 1 /* Specific PPC440EPx */
38#define CONFIG_4xx 1 /* ... PPC4xx family */
87dc0968
LJ		 39#define CONFIG_SYS_CLK_FREQ 33333333
40
214398d9
LJ		 41#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
87dc0968 43
214398d9 44/*
87dc0968 45 * Manufacturer's information serial EEPROM parameters
214398d9
LJ		 46 */
47#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
6433fa20
LJ		 48#define MAN_INFO_FIELD 2
49#define MAN_INFO_LENGTH 9
87dc0968 50#define MAN_MAC_ADDR_FIELD 3
6433fa20 51#define MAN_MAC_ADDR_LENGTH 12
87dc0968 52
214398d9
LJ		 53/*
54 * Base addresses -- Note these are effective addresses where the actual
55 * resources get mapped (not physical addresses).
56 */
6d0f6bcf
JCPV		 57#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
58#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
59
60#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
61#define CONFIG_SYS_FLASH0_SIZE 0x01000000
62#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
63#define CONFIG_SYS_FLASH1_TOP 0xF8000000
64#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
65#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
66#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
67#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
68#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
69#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
70#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
71#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
1095493a 72#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
87dc0968
LJ		 73
74/* Don't change either of these */
6d0f6bcf 75#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
87dc0968 76
6d0f6bcf
JCPV		 77#define CONFIG_SYS_USB2D0_BASE 0xe0000100
78#define CONFIG_SYS_USB_DEVICE 0xe0000000
79#define CONFIG_SYS_USB_HOST 0xe0000400
80#define CONFIG_SYS_CPLD_BASE 0xc0000000
87dc0968 81
214398d9 82/*
87dc0968 83 * Initial RAM & stack pointer
214398d9 84 */
87dc0968 85/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
6d0f6bcf
JCPV		 86#undef CONFIG_SYS_INIT_RAM_DCACHE
87#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
88#define CONFIG_SYS_INIT_RAM_END (4 << 10)
89#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
90#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
91#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
87dc0968 92
214398d9 93/*
87dc0968 94 * Serial Port
214398d9 95 */
6d0f6bcf 96#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
87dc0968
LJ		 97#define CONFIG_BAUDRATE 115200
98#define CONFIG_SERIAL_MULTI 1
99/* define this if you want console on UART1 */
100#undef CONFIG_UART1_CONSOLE
101
6d0f6bcf 102#define CONFIG_SYS_BAUDRATE_TABLE \
87dc0968
LJ		 103 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
104
214398d9 105/*
87dc0968 106 * Environment
214398d9 107 */
5a1aceb0 108#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
87dc0968 109
214398d9 110/*
87dc0968 111 * FLASH related
214398d9 112 */
6d0f6bcf 113#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a 114#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6433fa20 115#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
87dc0968 116
6d0f6bcf 117#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
87dc0968 118
6d0f6bcf
JCPV		 119#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
120#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
87dc0968 121
6d0f6bcf
JCPV		 122#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
123#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
87dc0968 124
6d0f6bcf
JCPV		 125#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
126#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
87dc0968 127
6d0f6bcf
JCPV		 128#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
129#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
87dc0968 130
0e8d1586 131#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf 132#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
0e8d1586 133#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
87dc0968 134
6433fa20 135/* Address and size of Redundant Environment Sector */
0e8d1586
JCPV		 136#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
137#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
87dc0968 138
214398d9 139/*
87dc0968 140 * DDR SDRAM
214398d9 141 */
214398d9
LJ		 142#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
143#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
144#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
145#define CONFIG_DDR_ECC /* Use ECC when available */
87dc0968
LJ		 146#define SPD_EEPROM_ADDRESS {0x50}
147#define CONFIG_PROG_SDRAM_TLB
a87fb1b3
LJ		 148#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
149 /* per 440EPx Errata CHIP_11 */
87dc0968 150
214398d9 151/*
87dc0968 152 * I2C
214398d9
LJ		 153 */
154#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
155#undef CONFIG_SOFT_I2C /* I2C bit-banged */
d0b0dcaa 156#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
6d0f6bcf
JCPV		 157#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
158#define CONFIG_SYS_I2C_SLAVE 0x7F
87dc0968 159
6d0f6bcf
JCPV		 160#define CONFIG_SYS_I2C_MULTI_EEPROMS
161#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
162#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
163#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
164#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
87dc0968
LJ		 165
166/* I2C RTC */
167#define CONFIG_RTC_M41T60 1
6d0f6bcf 168#define CONFIG_SYS_I2C_RTC_ADDR 0x68
87dc0968
LJ		 169
170/* I2C SYSMON (LM73) */
214398d9
LJ		 171#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
172#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
6d0f6bcf
JCPV		 173#define CONFIG_SYS_DTT_MAX_TEMP 70
174#define CONFIG_SYS_DTT_MIN_TEMP -30
87dc0968
LJ		 175
176#define CONFIG_PREBOOT "echo;" \
a87fb1b3 177 "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
87dc0968
LJ		 178 "echo"
179
180#undef CONFIG_BOOTARGS
181
182/* Setup some board specific values for the default environment variables */
183#define CONFIG_HOSTNAME korat
87dc0968 184
6433fa20 185/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
47ce4a28 186#define CONFIG_EXTRA_ENV_SETTINGS \
a87fb1b3
LJ		 187 "u_boot=korat/u-boot.bin\0" \
188 "load=tftp 200000 ${u_boot}\0" \
189 "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
190 "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
191 "F7F60000 F7FBFFFF\0" \
192 "upd=run load update\0" \
193 "bootfile=korat/uImage\0" \
194 "dtb=korat/korat.dtb\0" \
195 "kernel_addr=F4000000\0" \
196 "ramdisk_addr=F4400000\0" \
197 "dtb_addr=F41E0000\0" \
198 "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
199 "cp.b ${fileaddr} F4000000 ${filesize}\0" \
200 "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
201 "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
202 "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
203 "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
204 "${dtb}\0" \
205 "rd_size=73728\0" \
206 "ramargs=setenv bootargs root=/dev/ram rw " \
207 "ramdisk_size=${rd_size}\0" \
208 "usbdev=sda1\0" \
209 "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
210 "rootpath=/opt/eldk/ppc_4xxFP\0" \
87dc0968
LJ		 211 "netdev=eth0\0" \
212 "nfsargs=setenv bootargs root=/dev/nfs rw " \
213 "nfsroot=${serverip}:${rootpath}\0" \
a87fb1b3
LJ		 214 "pciclk=33\0" \
215 "addide=setenv bootargs ${bootargs} ide=reverse " \
216 "idebus=${pciclk}\0" \
87dc0968
LJ		 217 "addip=setenv bootargs ${bootargs} " \
218 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
219 ":${hostname}:${netdev}:off panic=1\0" \
220 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
a87fb1b3
LJ		 221 "flash_cf=run usbargs addide addip addtty; " \
222 "bootm ${kernel_addr} - ${dtb_addr}\0" \
223 "flash_nfs=run nfsargs addide addip addtty; " \
224 "bootm ${kernel_addr} - ${dtb_addr}\0" \
225 "flash_self=run ramargs addip addtty; " \
226 "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
87dc0968 227 ""
a87fb1b3
LJ		 228
229#define CONFIG_BOOTCOMMAND "run flash_cf"
87dc0968 230
214398d9 231#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
87dc0968 232
214398d9 233#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 234#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
87dc0968 235
96e21f86 236#define CONFIG_PPC4xx_EMAC
47ce4a28 237#define CONFIG_IBM_EMAC4_V4 1
214398d9
LJ		 238#define CONFIG_MII 1 /* MII PHY management */
239#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
87dc0968
LJ		 240#define CONFIG_PHY_DYNAMIC_ANEG 1
241
6433fa20 242#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
87dc0968
LJ		 243#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
244
245#define CONFIG_HAS_ETH0
6d0f6bcf 246#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
214398d9 247 /* buffers & descriptors */
87dc0968 248#define CONFIG_NET_MULTI 1
214398d9 249#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
87dc0968
LJ		 250#define CONFIG_PHY1_ADDR 3
251
252/* USB */
253#define CONFIG_USB_OHCI
254#define CONFIG_USB_STORAGE
255
256/* Comment this out to enable USB 1.1 device */
257#define USB_2_0_DEVICE
258
259/* Partitions */
260#define CONFIG_MAC_PARTITION
261#define CONFIG_DOS_PARTITION
262#define CONFIG_ISO_PARTITION
263
264/*
265 * BOOTP options
266 */
267#define CONFIG_BOOTP_BOOTFILESIZE
268#define CONFIG_BOOTP_BOOTPATH
269#define CONFIG_BOOTP_GATEWAY
270#define CONFIG_BOOTP_HOSTNAME
271#define CONFIG_BOOTP_SUBNETMASK
272
273/*
274 * Command line configuration.
275 */
276#include <config_cmd_default.h>
277
278#define CONFIG_CMD_ASKENV
279#define CONFIG_CMD_DATE
280#define CONFIG_CMD_DHCP
281#define CONFIG_CMD_DTT
282#define CONFIG_CMD_DIAG
283#define CONFIG_CMD_EEPROM
284#define CONFIG_CMD_ELF
285#define CONFIG_CMD_FAT
286#define CONFIG_CMD_I2C
87dc0968
LJ		 287#define CONFIG_CMD_IRQ
288#define CONFIG_CMD_MII
289#define CONFIG_CMD_NET
290#define CONFIG_CMD_NFS
291#define CONFIG_CMD_PCI
292#define CONFIG_CMD_PING
293#define CONFIG_CMD_REGINFO
294#define CONFIG_CMD_SDRAM
295#define CONFIG_CMD_USB
296
297/* POST support */
a87fb1b3
LJ		 298#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
299 CONFIG_SYS_POST_CPU | \
300 CONFIG_SYS_POST_ECC | \
301 CONFIG_SYS_POST_ETHER | \
302 CONFIG_SYS_POST_FPU | \
303 CONFIG_SYS_POST_I2C | \
304 CONFIG_SYS_POST_MEMORY | \
305 CONFIG_SYS_POST_RTC | \
306 CONFIG_SYS_POST_SPR | \
6d0f6bcf
JCPV		 307 CONFIG_SYS_POST_UART)
308
309#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
87dc0968 310#define CONFIG_LOGBUFFER
6d0f6bcf 311#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
87dc0968 312
6d0f6bcf 313#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
87dc0968
LJ		 314
315#define CONFIG_SUPPORT_VFAT
316
214398d9 317/*
87dc0968 318 * Miscellaneous configurable options
214398d9 319 */
6d0f6bcf
JCPV		 320#define CONFIG_SYS_LONGHELP /* undef to save memory */
321#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
87dc0968 322#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 323#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
87dc0968 324#else
6d0f6bcf 325#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
87dc0968 326#endif
6d0f6bcf 327#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
53677ef1 328 /* Print Buffer Size */
6d0f6bcf
JCPV		 329#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
330#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
87dc0968 331
6d0f6bcf
JCPV		 332#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
333#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
87dc0968 334
6d0f6bcf
JCPV		 335#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
336#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
87dc0968 337
6d0f6bcf 338#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
87dc0968 339
214398d9
LJ		 340#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
341#define CONFIG_LOOPW 1 /* enable loopw command */
342#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
343#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
344#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
87dc0968 345
6433fa20
LJ		 346/*
347 * Korat-specific options
348 */
6d0f6bcf 349#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
6433fa20 350
214398d9 351/*
87dc0968 352 * PCI stuff
214398d9 353 */
87dc0968 354/* General PCI */
214398d9
LJ		 355#define CONFIG_PCI /* include pci support */
356#define CONFIG_PCI_PNP /* do pci plug-and-play */
6d0f6bcf 357#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
214398d9 358#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf
JCPV		 359#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
360 /* CONFIG_SYS_PCI_MEMBASE */
87dc0968 361/* Board-specific PCI */
6d0f6bcf
JCPV		 362#define CONFIG_SYS_PCI_TARGET_INIT
363#define CONFIG_SYS_PCI_MASTER_INIT
a760b020 364#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
87dc0968 365
6d0f6bcf
JCPV		 366#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
367#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
87dc0968
LJ		 368
369/*
214398d9
LJ		 370 * For booting Linux, the board info and command line data have to be in the
371 * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
372 * during initialization.
87dc0968 373 */
6d0f6bcf 374#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
87dc0968 375
214398d9 376/*
87dc0968 377 * External Bus Controller (EBC) Setup
214398d9 378 */
87dc0968
LJ		 379
380/* Memory Bank 0 (NOR-FLASH) initialization */
6d0f6bcf
JCPV		 381#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
382#define CONFIG_SYS_EBC_PB0AP 0x04017300
383#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
384#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
385#define CONFIG_SYS_EBC_PB0AP 0x04017300
386#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
6433fa20 387#else
6d0f6bcf 388#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
6433fa20 389#endif
87dc0968
LJ		 390
391/* Memory Bank 1 (NOR-FLASH) initialization */
6d0f6bcf
JCPV		 392#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
393#define CONFIG_SYS_EBC_PB1AP 0x04017300
394#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
6433fa20 395#else
6d0f6bcf 396#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
6433fa20 397#endif
87dc0968
LJ		 398
399/* Memory Bank 2 (CPLD) initialization */
6d0f6bcf
JCPV		 400#define CONFIG_SYS_EBC_PB2AP 0x04017300
401#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
87dc0968 402
214398d9 403/*
0ddd969a
LJ		 404 * GPIO Setup
405 *
406 * Korat GPIO usage:
407 *
408 * Init.
409 * Pin Source I/O value Function
410 * ------ ------ --- ----- ---------------------------------
411 * GPIO00 Alt1 I/O x PerAddr07
412 * GPIO01 Alt1 I/O x PerAddr06
413 * GPIO02 Alt1 I/O x PerAddr05
414 * GPIO03 GPIO x x GPIO03 to expansion bus connector
415 * GPIO04 GPIO x x GPIO04 to expansion bus connector
416 * GPIO05 GPIO x x GPIO05 to expansion bus connector
417 * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
418 * GPIO07 Alt1 O x PerCS2 (CPLD)
419 * GPIO08 Alt1 O x PerCS3 to expansion bus connector
420 * GPIO09 Alt1 O x PerCS4 to expansion bus connector
421 * GPIO10 Alt1 O x PerCS5 to expansion bus connector
422 * GPIO11 Alt1 I x PerErr
423 * GPIO12 GPIO O 0 ATMega !Reset
a87fb1b3 424 * GPIO13 GPIO x x Test Point 2 (TP2)
0ddd969a
LJ		 425 * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
426 * GPIO15 GPIO O 0 CPU Run LED !On
427 * GPIO16 Alt1 O x GMC1TxD0
428 * GPIO17 Alt1 O x GMC1TxD1
429 * GPIO18 Alt1 O x GMC1TxD2
430 * GPIO19 Alt1 O x GMC1TxD3
431 * GPIO20 Alt1 I x RejectPkt0
432 * GPIO21 Alt1 I x RejectPkt1
433 * GPIO22 GPIO I x PGOOD_DDR
434 * GPIO23 Alt1 O x SCPD0
435 * GPIO24 Alt1 O x GMC0TxD2
436 * GPIO25 Alt1 O x GMC0TxD3
437 * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
438 * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
439 * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
440 * GPIO29 GPIO I x Test jumper !Present
441 * GPIO30 GPIO I x SFP module #0 !Present
442 * GPIO31 GPIO I x SFP module #1 !Present
443 *
444 * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
445 * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
446 * GPIO34 Alt2 I x !UART1_CTS
447 * GPIO35 Alt2 O x !UART1_RTS
448 * GPIO36 Alt1 I x !UART0_CTS
449 * GPIO37 Alt1 O x !UART0_RTS
450 * GPIO38 Alt2 O x UART1_Tx
451 * GPIO39 Alt2 I x UART1_Rx
452 * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
453 * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
454 * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
455 * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
456 * GPIO44 xxxx x x (grounded through pulldown)
457 * GPIO45 GPIO O 0 PHY #0 Enable
458 * GPIO46 GPIO O 0 PHY #1 Enable
459 * GPIO47 GPIO I x Reset switch !Pressed
460 * GPIO48 GPIO I x Shutdown switch !Pressed
461 * GPIO49 xxxx x x (reserved for trace port)
462 * . . . . .
463 * . . . . .
464 * . . . . .
465 * GPIO63 xxxx x x (reserved for trace port)
214398d9 466 */
0ddd969a 467
6d0f6bcf
JCPV		 468#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
469#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
470#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
471#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
472#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
473#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
474#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
475#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
476#define CONFIG_SYS_GPIO_PHY0_EN 45
477#define CONFIG_SYS_GPIO_PHY1_EN 46
478#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
0ddd969a 479
214398d9 480/*
0ddd969a
LJ		 481 * PPC440 GPIO Configuration
482 */
6d0f6bcf 483#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
0ddd969a
LJ		 484{ \
485/* GPIO Core 0 */ \
486{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
487{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
488{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
489{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
490{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
491{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
492{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
493{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
494{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
495{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
496{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
497{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
498{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
a87fb1b3 499{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
0ddd969a
LJ		 500{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
501{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
502{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
503{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
504{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
505{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
506{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
507{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
508{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
509{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
510{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
511{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
512{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
513{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
514{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
515{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
516{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
517{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
518}, \
519{ \
520/* GPIO Core 1 */ \
521{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
522{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
523{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
524{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
525{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
526{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
527{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
528{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
529{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
530{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
531{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
532{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
533{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
534{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
535{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
536{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
537{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
538{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
539{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
540{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
541{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
542{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
543{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
544{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
545{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
546{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
547{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
548{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
549{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
550{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
551{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
552{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
553} \
554}
555
87dc0968
LJ		 556/*
557 * Internal Definitions
558 *
559 * Boot Flags
560 */
214398d9
LJ		 561#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
562#define BOOTFLAG_WARM 0x02 /* Software reboot */
87dc0968
LJ		 563
564#if defined(CONFIG_CMD_KGDB)
214398d9
LJ		 565#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
566#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
87dc0968 567#endif
214398d9 568
47ce4a28
LJ		 569/* Pass open firmware flat tree */
570#define CONFIG_OF_LIBFDT 1
571#define CONFIG_OF_BOARD_SETUP 1
572
87dc0968 573#endif /* __CONFIG_H */
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