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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
8d811ca3 NI |
2 | /* |
3 | * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
8d811ca3 NI |
5 | */ |
6 | ||
7 | #ifndef __KZM9G_H | |
8 | #define __KZM9G_H | |
9 | ||
8d811ca3 | 10 | #define CONFIG_SH73A0 |
8d811ca3 NI |
11 | #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G |
12 | ||
13 | #include <asm/arch/rmobile.h> | |
14 | ||
15 | #define CONFIG_ARCH_CPU_INIT | |
8d811ca3 | 16 | |
8d811ca3 NI |
17 | #define CONFIG_CMDLINE_TAG |
18 | #define CONFIG_SETUP_MEMORY_TAGS | |
19 | #define CONFIG_INITRD_TAG | |
8d811ca3 | 20 | |
8d811ca3 NI |
21 | /* MEMORY */ |
22 | #define KZM_SDRAM_BASE (0x40000000) | |
23 | #define PHYS_SDRAM KZM_SDRAM_BASE | |
24 | #define PHYS_SDRAM_SIZE (512 * 1024 * 1024) | |
8d811ca3 NI |
25 | |
26 | /* NOR Flash */ | |
27 | #define KZM_FLASH_BASE (0x00000000) | |
28 | #define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) | |
29 | #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) | |
30 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) | |
31 | #define CONFIG_SYS_MAX_FLASH_SECT (512) | |
32 | ||
33 | /* prompt */ | |
8d811ca3 | 34 | #define CONFIG_SYS_PBSIZE 256 |
8d811ca3 NI |
35 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
36 | ||
37 | /* SCIF */ | |
8d811ca3 | 38 | #define CONFIG_CONS_SCIF4 |
8d811ca3 NI |
39 | |
40 | #define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) | |
41 | #define CONFIG_SYS_MEMTEST_END \ | |
42 | (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
8d811ca3 NI |
43 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
44 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE | |
45 | ||
46 | #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ | |
47 | #define CONFIG_SYS_INIT_RAM_SIZE (0x10000) | |
48 | #define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) | |
49 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
50 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
51 | GENERATED_GBL_DATA_SIZE) | |
9415cf93 TK |
52 | #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) |
53 | #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) | |
54 | #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) | |
8d811ca3 NI |
55 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
56 | ||
57 | #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) | |
58 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) | |
8d811ca3 NI |
59 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
60 | ||
8d811ca3 NI |
61 | #define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 |
62 | ||
63 | /* FLASH */ | |
8d811ca3 NI |
64 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
65 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
66 | #define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ | |
67 | #define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE | |
68 | #define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE | |
69 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) | |
70 | ||
71 | /* Timeout for Flash erase operations (in ms) */ | |
72 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) | |
73 | /* Timeout for Flash write operations (in ms) */ | |
74 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) | |
75 | /* Timeout for Flash set sector lock bit operations (in ms) */ | |
76 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) | |
77 | /* Timeout for Flash clear lock bit operations (in ms) */ | |
78 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) | |
79 | ||
8d811ca3 | 80 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
8d811ca3 NI |
81 | |
82 | /* GPIO / PFC */ | |
83 | #define CONFIG_SH_GPIO_PFC | |
84 | ||
85 | /* Clock */ | |
eae6c8ab | 86 | #define CONFIG_GLOBAL_TIMER |
8d811ca3 NI |
87 | #define CONFIG_SYS_CLK_FREQ (48000000) |
88 | #define CONFIG_SYS_CPU_CLK (1196000000) | |
59562ff6 | 89 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
8d811ca3 | 90 | #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ |
8d811ca3 | 91 | |
38263df8 | 92 | #define CONFIG_NFS_TIMEOUT 10000UL |
8d811ca3 NI |
93 | |
94 | /* I2C */ | |
2035d77d NI |
95 | #define CONFIG_SYS_I2C |
96 | #define CONFIG_SYS_I2C_SH | |
97 | #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 | |
98 | #define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 | |
99 | #define CONFIG_SYS_I2C_SH_SPEED0 100000 | |
100 | #define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 | |
101 | #define CONFIG_SYS_I2C_SH_SPEED1 100000 | |
102 | #define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 | |
103 | #define CONFIG_SYS_I2C_SH_SPEED2 100000 | |
104 | #define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 | |
105 | #define CONFIG_SYS_I2C_SH_SPEED3 100000 | |
106 | #define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 | |
107 | #define CONFIG_SYS_I2C_SH_SPEED4 100000 | |
b1af67fe | 108 | #define CONFIG_SH_I2C_8BIT |
2035d77d NI |
109 | #define CONFIG_SH_I2C_DATA_HIGH 4 |
110 | #define CONFIG_SH_I2C_DATA_LOW 5 | |
111 | #define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ | |
8d811ca3 NI |
112 | |
113 | #endif /* __KZM9G_H */ |