[thirdparty/u-boot.git] / include / configs / lager.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * include/configs/lager.h
 *     This file is lager board configuration.
 *
 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
 */

#ifndef __LAGER_H
#define __LAGER_H

#include "rcar-gen2-common.h"

#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
#define STACK_AREA_SIZE			0x00100000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootm_size=0x10000000\0"

/* SPL support */
#define CONFIG_SPL_STACK		0xe6340000
#define CONFIG_SPL_MAX_SIZE		0x4000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF0
#define CONFIG_SH_SCIF_CLK_FREQ		65000000
#endif

#endif	/* __LAGER_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
f4ec4522 NI	2	/*
	3	* include/configs/lager.h
	4	* This file is lager board configuration.
	5	*
5ca6dfe6	6	* Copyright (C) 2013, 2014 Renesas Electronics Corporation
f4ec4522 NI	7	*/
	8
	9	#ifndef __LAGER_H
	10	#define __LAGER_H
	11
5ca6dfe6	12	#include "rcar-gen2-common.h"
d80149b2	13
e6027e6f MV	14	#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
	15	#define STACK_AREA_SIZE 0x00100000
	16	#define LOW_LEVEL_MERAM_STACK \
f4ec4522 NI	17	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	18
	19	/* MEMORY */
5ca6dfe6 NI	20	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	21	#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
	22	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
f4ec4522	23
23565c6b	24	/* SH Ether */
23565c6b NI	25	#define CONFIG_SH_ETHER_USE_PORT 0
	26	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	27	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
23565c6b NI	28	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
23565c6b NI	29	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
e6027e6f	30	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
23565c6b NI	31	#define CONFIG_BITBANGMII_MULTI
23565c6b NI	32
f4ec4522	33	/* Board Clock */
b1f78a2e NI	34	#define RMOBILE_XTAL_CLK 20000000u
b1f78a2e NI	35	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
f4ec4522	36
e6027e6f	37	#define CONFIG_EXTRA_ENV_SETTINGS \
07a8060a	38	"bootm_size=0x10000000\0"
e6027e6f MV	39
e6027e6f MV	40	/* SPL support */
e6027e6f MV	41	#define CONFIG_SPL_STACK 0xe6340000
e6027e6f MV	42	#define CONFIG_SPL_MAX_SIZE 0x4000
e6027e6f MV	43	#ifdef CONFIG_SPL_BUILD
	44	#define CONFIG_CONS_SCIF0
	45	#define CONFIG_SH_SCIF_CLK_FREQ 65000000
	46	#endif
acdfecbb	47
f4ec4522	48	#endif /* __LAGER_H */