projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 61525f2f GL |
1 | /* |
| 2 | * Copyright (C) 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License as | |
| 6 | * published by the Free Software Foundation; either version 2 of | |
| 7 | * the License, or (at your option) any later version. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program; if not, write to the Free Software | |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 17 | * MA 02111-1307 USA | |
| 18 | */ | |
| 19 | ||
| 20 | #ifndef __CONFIG_H | |
| 21 | #define __CONFIG_H | |
| 22 | ||
| 2ae18241 WD |
23 | /* |
| 24 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
| 25 | * | |
| 26 | * Standard configuration - all models | |
| 27 | * 0xFFF00000 boot from flash | |
| 28 | * | |
| 29 | * Test configuration (boot from RAM using uloader.o) | |
| 30 | * LinkStation HD-HLAN and KuroBox Standard | |
| 31 | * 0x03F00000 boot from RAM | |
| 32 | * LinkStation HD-HGLAN and KuroBox HG | |
| 33 | * 0x07F00000 boot from RAM | |
| 34 | */ | |
| 35 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 36 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
| 37 | #endif | |
| 38 | ||
| 61525f2f GL |
39 | #if 0 |
| 40 | #define DEBUG | |
| 41 | #endif | |
| 42 | ||
| 43 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
| 44 | ||
| 45 | /*----------------------------------------------------------------------- | |
| 46 | * User configurable settings: | |
| 47 | * Mandatory settings: | |
| 48 | * CONFIG_IPADDR_LS - the IP address of the LinkStation | |
| 49 | * CONFIG_SERVERIP_LS - the address of the server for NFS/TFTP/DHCP/BOOTP | |
| 50 | * Optional settins: | |
| 51 | * CONFIG_NCIP_LS - the adress of the computer running net console | |
| 52 | * if not configured, it will be set to | |
| 53 | * CONFIG_SERVERIP_LS | |
| 54 | */ | |
| 55 | ||
| 56 | ||
| 57 | #define CONFIG_IPADDR_LS 192.168.11.150 | |
| 58 | #define CONFIG_SERVERIP_LS 192.168.11.149 | |
| 59 | ||
| 60 | #if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS) | |
| 61 | #error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined | |
| 62 | #endif | |
| 63 | ||
| 64 | #if !defined(CONFIG_NCIP_LS) | |
| 65 | #define CONFIG_NCIP_LS CONFIG_SERVERIP_LS | |
| 66 | #endif | |
| 67 | ||
| 68 | /*---------------------------------------------------------------------- | |
| 69 | * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING | |
| 70 | *---------------------------------------------------------------------*/ | |
| 71 | ||
| 72 | #define CONFIG_MPC8245 1 | |
| 73 | #define CONFIG_LINKSTATION 1 | |
| 74 | ||
| 75 | /*--------------------------------------- | |
| 76 | * Supported models | |
| 77 | * | |
| 78 | * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN) | |
| 79 | * LinkStation old model (CONFIG_LAN) - totally untested | |
| 80 | * LinkStation HGLAN / KuroBox HG (CONFIG_HGLAN) | |
| 81 | * | |
| 82 | * Models not supported yet | |
| 83 | * TeraStatin (CONFIG_HTGL) | |
| 84 | */ | |
| 85 | ||
| 86 | #if defined(CONFIG_HLAN) || defined(CONFIG_LAN) | |
| 87 | #define CONFIG_IDENT_STRING " LinkStation / KuroBox" | |
| 88 | #elif defined(CONFIG_HGLAN) | |
| 89 | #define CONFIG_IDENT_STRING " LinkStation HG / KuroBox HG" | |
| 90 | #elif defined(CONFIG_HTGL) | |
| 91 | #define CONFIG_IDENT_STRING " TeraStation" | |
| 92 | #else | |
| 93 | #error No LinkStation model defined | |
| 94 | #endif | |
| 95 | ||
| 96 | #define CONFIG_BOOTDELAY 5 | |
| 97 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 98 | #undef CONFIG_BOOT_RETRY_TIME | |
| 99 | ||
| 100 | #define CONFIG_AUTOBOOT_KEYED | |
| c37207d7 WD |
101 | #define CONFIG_AUTOBOOT_PROMPT \ |
| 102 | "Boot in %02d seconds ('s' to stop)...", bootdelay | |
| 61525f2f GL |
103 | #define CONFIG_AUTOBOOT_STOP_STR "s" |
| 104 | ||
| 105 | #define CONFIG_CMD_IDE | |
| 106 | #define CONFIG_CMD_PCI | |
| 107 | #define CONFIG_CMD_DHCP | |
| 108 | #define CONFIG_CMD_PING | |
| 109 | #define CONFIG_CMD_EXT2 | |
| 110 | ||
| 111 | #define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL | |
| 112 | ||
| 113 | #define CONFIG_OF_LIBFDT 1 | |
| 114 | ||
| 61525f2f GL |
115 | #define OF_STDOUT_PATH "/soc10x/serial@80004600" |
| 116 | ||
| 117 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 118 | #include <config_cmd_default.h> | |
| 119 | ||
| 120 | /* | |
| 121 | * Miscellaneous configurable options | |
| 122 | */ | |
| 6d0f6bcf JCPV |
123 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 124 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 125 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 61525f2f | 126 | |
| 6d0f6bcf JCPV |
127 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 128 | #define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ | |
| 129 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 130 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */ | |
| 61525f2f | 131 | |
| 53677ef1 | 132 | #define CONFIG_BOOTCOMMAND "run bootcmd1" |
| 61525f2f | 133 | #define CONFIG_BOOTARGS "root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug" |
| 53677ef1 | 134 | #define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" |
| 61525f2f | 135 | |
| 6d0f6bcf | 136 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| 61525f2f GL |
137 | |
| 138 | #define XMK_STR(x) #x | |
| 139 | #define MK_STR(x) XMK_STR(x) | |
| 140 | ||
| 141 | #if defined(CONFIG_HLAN) || defined(CONFIG_LAN) | |
| 142 | #define UBFILE "share/u-boot/u-boot-hd.flash.bin" | |
| 143 | #elif defined(CONFIG_HGLAN) | |
| 144 | #define UBFILE "share/u-boot/u-boot-hg.flash.bin" | |
| 145 | #elif defined(CONFIG_HTGL) | |
| 146 | #define UBFILE "share/u-boot/u-boot-ht.flash.bin" | |
| 147 | #else | |
| 148 | #error No LinkStation model defined | |
| 149 | #endif | |
| 150 | ||
| 151 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 152 | "autoload=no\0" \ | |
| 153 | "stdin=nc\0" \ | |
| 154 | "stdout=nc\0" \ | |
| 155 | "stderr=nc\0" \ | |
| 156 | "ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0" \ | |
| 157 | "netmask=255.255.255.0\0" \ | |
| 158 | "serverip="MK_STR(CONFIG_SERVERIP_LS)"\0" \ | |
| 159 | "ncip="MK_STR(CONFIG_NCIP_LS)"\0" \ | |
| 160 | "netretry=no\0" \ | |
| 161 | "nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \ | |
| 162 | "ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \ | |
| 163 | "ldaddr=800000\0" \ | |
| 164 | "hdpart=0:1\0" \ | |
| 165 | "hdfile=boot/uImage\0" \ | |
| 166 | "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0" \ | |
| 167 | "boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0" \ | |
| 168 | "hdboot=run hdload;run boothd\0" \ | |
| 169 | "flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \ | |
| 170 | "emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \ | |
| 171 | "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
| 172 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ | |
| 173 | "bootretry=30\0" \ | |
| 174 | "bootcmd1=run hdboot;run flboot\0" \ | |
| 175 | "bootcmd2=run flboot\0" \ | |
| 176 | "bootcmd3=run emboot\0" \ | |
| 177 | "writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \ | |
| 178 | "writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \ | |
| 179 | "ubpart=0:3\0" \ | |
| 180 | "ubfile="UBFILE"\0" \ | |
| 181 | "ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \ | |
| 182 | "ubsaddr=fff00000\0" \ | |
| 183 | "ubeaddr=fff2ffff\0" \ | |
| 184 | "ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \ | |
| 185 | "upgrade=run ubload ubflash\0" | |
| 186 | ||
| 187 | /*----------------------------------------------------------------------- | |
| 188 | * PCI stuff | |
| 189 | */ | |
| 190 | #define CONFIG_PCI | |
| 191 | /* Verified: CONFIG_PCI_PNP doesn't work */ | |
| 192 | #undef CONFIG_PCI_PNP | |
| 193 | #define CONFIG_PCI_SCAN_SHOW | |
| 194 | ||
| 195 | #ifndef CONFIG_PCI_PNP | |
| 196 | /* Keep the following defines in sync with the BAT mappings */ | |
| 197 | ||
| 198 | #define PCI_ETH_IOADDR 0xbfff00 | |
| 199 | #define PCI_ETH_MEMADDR 0xbffffc00 | |
| 200 | #define PCI_IDE_IOADDR 0xbffed0 | |
| 201 | #define PCI_IDE_MEMADDR 0xbffffb00 | |
| 202 | #define PCI_USB0_IOADDR 0 | |
| 203 | #define PCI_USB0_MEMADDR 0xbfffe000 | |
| 204 | #define PCI_USB1_IOADDR 0 | |
| 205 | #define PCI_USB1_MEMADDR 0xbfffd000 | |
| 206 | #define PCI_USB2_IOADDR 0 | |
| 207 | #define PCI_USB2_MEMADDR 0xbfffcf00 | |
| 208 | ||
| 209 | #endif | |
| 210 | ||
| 211 | /*----------------------------------------------------------------------- | |
| 212 | * Ethernet stuff | |
| 213 | */ | |
| 214 | #define CONFIG_NET_MULTI | |
| 215 | ||
| 216 | #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) | |
| 217 | #define CONFIG_TULIP | |
| 218 | #define CONFIG_TULIP_USE_IO | |
| 219 | #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) | |
| 220 | #define CONFIG_RTL8169 | |
| 221 | #endif | |
| 222 | ||
| 223 | #define CONFIG_NET_RETRY_COUNT 5 | |
| 224 | ||
| 225 | #define CONFIG_NETCONSOLE | |
| 226 | ||
| 227 | /*----------------------------------------------------------------------- | |
| 228 | * Start addresses for the final memory configuration | |
| 229 | * (Set up by the startup code) | |
| 6d0f6bcf | 230 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 61525f2f | 231 | */ |
| 6d0f6bcf | 232 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 61525f2f | 233 | |
| 6d0f6bcf JCPV |
234 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 |
| 235 | #define CONFIG_SYS_FLASH_SIZE 0x00400000 | |
| 14d0a02a | 236 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 61525f2f | 237 | |
| 6d0f6bcf JCPV |
238 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
| 239 | #define CONFIG_SYS_EUMB_ADDR 0x80000000 | |
| 240 | #define CONFIG_SYS_PCI_MEM_ADDR 0xB0000000 | |
| 241 | #define CONFIG_SYS_MISC_REGION_ADDR 0xFE000000 | |
| 61525f2f | 242 | |
| 6d0f6bcf JCPV |
243 | #define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256 kB */ |
| 244 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ | |
| 61525f2f | 245 | |
| 6d0f6bcf JCPV |
246 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
| 247 | #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ | |
| 61525f2f GL |
248 | |
| 249 | /* Maximum amount of RAM */ | |
| 250 | #if defined(CONFIG_HLAN) || defined(CONFIG_LAN) | |
| 6d0f6bcf | 251 | #define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */ |
| 61525f2f | 252 | #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) |
| 6d0f6bcf | 253 | #define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */ |
| 61525f2f GL |
254 | #else |
| 255 | #error Unknown LinkStation type | |
| 256 | #endif | |
| 257 | ||
| 258 | /*----------------------------------------------------------------------- | |
| 14d0a02a | 259 | * Change CONFIG_SYS_TEXT_BASE in bord/linkstation/config.mk to get a RAM build |
| 61525f2f GL |
260 | * |
| 261 | * RAM based builds are for testing purposes. A Linux module, uloader.o, | |
| 262 | * exists to load U-Boot and pass control to it | |
| 263 | * | |
| 264 | * Always do "make clean" after changing the build type | |
| 265 | */ | |
| 6d0f6bcf JCPV |
266 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE |
| 267 | #define CONFIG_SYS_RAMBOOT | |
| 61525f2f GL |
268 | #endif |
| 269 | ||
| 270 | /*----------------------------------------------------------------------- | |
| 271 | * Definitions for initial stack pointer and data area | |
| 272 | */ | |
| 273 | #if 1 /* RAM is available when the first C function is called */ | |
| 6d0f6bcf | 274 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 0x1000) |
| 61525f2f | 275 | #else |
| 6d0f6bcf | 276 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
| 61525f2f | 277 | #endif |
| 553f0982 | 278 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
| 25ddd1fb | 279 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 61525f2f GL |
280 | |
| 281 | /*---------------------------------------------------------------------- | |
| 282 | * Serial configuration | |
| 283 | */ | |
| 284 | #define CONFIG_CONS_INDEX 1 | |
| 285 | #define CONFIG_BAUDRATE 57600 | |
| 6d0f6bcf | 286 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 61525f2f | 287 | |
| 6d0f6bcf JCPV |
288 | #define CONFIG_SYS_NS16550 |
| 289 | #define CONFIG_SYS_NS16550_SERIAL | |
| 61525f2f | 290 | |
| 6d0f6bcf | 291 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 61525f2f | 292 | |
| 6d0f6bcf | 293 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| 61525f2f | 294 | |
| 6d0f6bcf JCPV |
295 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4600) /* Console port */ |
| 296 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4500) /* AVR port */ | |
| 61525f2f GL |
297 | |
| 298 | /* | |
| 299 | * Low Level Configuration Settings | |
| 300 | * (address mappings, register initial values, etc.) | |
| 301 | * You should know what you are doing if you make changes here. | |
| 302 | * For the detail description refer to the MPC8245 user's manual. | |
| 303 | * | |
| 304 | * Unless indicated otherwise, the values are | |
| 305 | * taken from the orignal Linkstation boot code | |
| 306 | * | |
| 307 | * Most of the low level configuration setttings are normally used | |
| a47a12be | 308 | * in arch/powerpc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation. |
| 61525f2f GL |
309 | * Low level initialisation is done in board/linkstation/early_init.S |
| 310 | * The values below are included for reference purpose only | |
| 311 | */ | |
| 312 | ||
| 313 | /* FIXME: 32.768 MHz is the crystal frequency but */ | |
| 314 | /* the real frequency is lower by about 0.75% */ | |
| 315 | #define CONFIG_SYS_CLK_FREQ 32768000 | |
| 6d0f6bcf | 316 | #define CONFIG_SYS_HZ 1000 |
| 61525f2f GL |
317 | |
| 318 | /* Bit-field values for MCCR1. */ | |
| 6d0f6bcf JCPV |
319 | #define CONFIG_SYS_ROMNAL 0 |
| 320 | #define CONFIG_SYS_ROMFAL 11 | |
| 321 | ||
| 322 | #define CONFIG_SYS_BANK0_ROW 2 /* Only bank 0 used: 13 x n x 4 */ | |
| 323 | #define CONFIG_SYS_BANK1_ROW 0 | |
| 324 | #define CONFIG_SYS_BANK2_ROW 0 | |
| 325 | #define CONFIG_SYS_BANK3_ROW 0 | |
| 326 | #define CONFIG_SYS_BANK4_ROW 0 | |
| 327 | #define CONFIG_SYS_BANK5_ROW 0 | |
| 328 | #define CONFIG_SYS_BANK6_ROW 0 | |
| 329 | #define CONFIG_SYS_BANK7_ROW 0 | |
| 61525f2f GL |
330 | |
| 331 | /* Bit-field values for MCCR2. */ | |
| 6d0f6bcf | 332 | #define CONFIG_SYS_TSWAIT 0 |
| 61525f2f | 333 | #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) |
| 6d0f6bcf | 334 | #define CONFIG_SYS_REFINT 0x15e0 |
| 61525f2f | 335 | #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) |
| 6d0f6bcf | 336 | #define CONFIG_SYS_REFINT 0x1580 |
| 61525f2f GL |
337 | #endif |
| 338 | ||
| 339 | /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ | |
| 6d0f6bcf | 340 | #define CONFIG_SYS_BSTOPRE 0x91c |
| 61525f2f GL |
341 | |
| 342 | /* Bit-field values for MCCR3. */ | |
| 6d0f6bcf | 343 | #define CONFIG_SYS_REFREC 7 |
| 61525f2f GL |
344 | |
| 345 | /* Bit-field values for MCCR4. */ | |
| 6d0f6bcf JCPV |
346 | #define CONFIG_SYS_PRETOACT 2 |
| 347 | #define CONFIG_SYS_ACTTOPRE 2 /* Original value was 2 */ | |
| 348 | #define CONFIG_SYS_ACTORW 2 | |
| 61525f2f | 349 | #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) |
| 6d0f6bcf JCPV |
350 | #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* For 100MHz bus */ |
| 351 | /*#define CONFIG_SYS_SDMODE_BURSTLEN 3*/ | |
| 61525f2f | 352 | #elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) |
| 6d0f6bcf JCPV |
353 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* For 133MHz bus */ |
| 354 | /*#define CONFIG_SYS_SDMODE_BURSTLEN 2*/ | |
| 61525f2f | 355 | #endif |
| 6d0f6bcf JCPV |
356 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
| 357 | #define CONFIG_SYS_EXTROM 1 /* Original setting but there is no EXTROM */ | |
| 358 | #define CONFIG_SYS_REGDIMM 0 | |
| 359 | #define CONFIG_SYS_DBUS_SIZE2 1 | |
| 360 | #define CONFIG_SYS_SDMODE_WRAP 0 | |
| 61525f2f | 361 | |
| 6d0f6bcf JCPV |
362 | #define CONFIG_SYS_PGMAX 0x32 /* All boards use this setting. Original 0x92 */ |
| 363 | #define CONFIG_SYS_SDRAM_DSCD 0x30 | |
| 61525f2f GL |
364 | |
| 365 | /* Memory bank settings. | |
| 366 | * Only bits 20-29 are actually used from these vales to set the | |
| 367 | * start/end addresses. The upper two bits will always be 0, and the lower | |
| 368 | * 20 bits will be 0x00000 for a start address, or 0xfffff for an end | |
| 369 | * address. Refer to the MPC8240 book. | |
| 370 | */ | |
| 371 | ||
| 6d0f6bcf JCPV |
372 | #define CONFIG_SYS_BANK0_START 0x00000000 |
| 373 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) | |
| 374 | #define CONFIG_SYS_BANK0_ENABLE 1 | |
| 375 | #define CONFIG_SYS_BANK1_START 0x3ff00000 | |
| 376 | #define CONFIG_SYS_BANK1_END 0x3fffffff | |
| 377 | #define CONFIG_SYS_BANK1_ENABLE 0 | |
| 378 | #define CONFIG_SYS_BANK2_START 0x3ff00000 | |
| 379 | #define CONFIG_SYS_BANK2_END 0x3fffffff | |
| 380 | #define CONFIG_SYS_BANK2_ENABLE 0 | |
| 381 | #define CONFIG_SYS_BANK3_START 0x3ff00000 | |
| 382 | #define CONFIG_SYS_BANK3_END 0x3fffffff | |
| 383 | #define CONFIG_SYS_BANK3_ENABLE 0 | |
| 384 | #define CONFIG_SYS_BANK4_START 0x3ff00000 | |
| 385 | #define CONFIG_SYS_BANK4_END 0x3fffffff | |
| 386 | #define CONFIG_SYS_BANK4_ENABLE 0 | |
| 387 | #define CONFIG_SYS_BANK5_START 0x3ff00000 | |
| 388 | #define CONFIG_SYS_BANK5_END 0x3fffffff | |
| 389 | #define CONFIG_SYS_BANK5_ENABLE 0 | |
| 390 | #define CONFIG_SYS_BANK6_START 0x3ff00000 | |
| 391 | #define CONFIG_SYS_BANK6_END 0x3fffffff | |
| 392 | #define CONFIG_SYS_BANK6_ENABLE 0 | |
| 393 | #define CONFIG_SYS_BANK7_START 0x3ff00000 | |
| 394 | #define CONFIG_SYS_BANK7_END 0x3fffffff | |
| 395 | #define CONFIG_SYS_BANK7_ENABLE 0 | |
| 396 | ||
| 397 | #define CONFIG_SYS_ODCR 0x15 | |
| 61525f2f GL |
398 | |
| 399 | /*---------------------------------------------------------------------- | |
| 400 | * Initial BAT mappings | |
| 401 | */ | |
| 402 | ||
| 403 | /* NOTES: | |
| 404 | * 1) GUARDED and WRITETHROUGH not allowed in IBATS | |
| 405 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
| 406 | */ | |
| 407 | ||
| 408 | /* SDRAM */ | |
| 6d0f6bcf JCPV |
409 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 410 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) | |
| 61525f2f | 411 | |
| 6d0f6bcf JCPV |
412 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
| 413 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 61525f2f GL |
414 | |
| 415 | /* EUMB: 1MB of address space */ | |
| 6d0f6bcf JCPV |
416 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) |
| 417 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 61525f2f | 418 | |
| 6d0f6bcf JCPV |
419 | #define CONFIG_SYS_DBAT1L (CONFIG_SYS_IBAT1L | BATL_GUARDEDSTORAGE) |
| 420 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 61525f2f GL |
421 | |
| 422 | /* PCI Mem: 256MB of address space */ | |
| 6d0f6bcf JCPV |
423 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) |
| 424 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 61525f2f | 425 | |
| 6d0f6bcf JCPV |
426 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_IBAT2L | BATL_GUARDEDSTORAGE) |
| 427 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 61525f2f GL |
428 | |
| 429 | /* PCI and local ROM/Flash: last 32MB of address space */ | |
| 6d0f6bcf JCPV |
430 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) |
| 431 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 61525f2f | 432 | |
| 6d0f6bcf JCPV |
433 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_IBAT3L | BATL_GUARDEDSTORAGE) |
| 434 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 61525f2f GL |
435 | |
| 436 | /* | |
| 437 | * For booting Linux, the board info and command line data | |
| 438 | * have to be in the first 8 MB of memory, since this is | |
| 439 | * the maximum mapped by the Linux kernel during initialization. | |
| 440 | * | |
| 441 | * FIXME: This doesn't appear to be true for the newer kernels | |
| 442 | * which map more that 8 MB | |
| 443 | */ | |
| 6d0f6bcf | 444 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 61525f2f GL |
445 | |
| 446 | /*----------------------------------------------------------------------- | |
| 447 | * FLASH organization | |
| 448 | */ | |
| 6d0f6bcf | 449 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| 00b1883a | 450 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 61525f2f | 451 | |
| 6d0f6bcf JCPV |
452 | #undef CONFIG_SYS_FLASH_PROTECTION |
| 453 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
| 454 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ | |
| 455 | #define CONFIG_SYS_MAX_FLASH_SECT 72 /* Max number of sectors per flash */ | |
| 61525f2f | 456 | |
| 6d0f6bcf JCPV |
457 | #define CONFIG_SYS_FLASH_ERASE_TOUT 12000 |
| 458 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 | |
| 61525f2f | 459 | |
| 6d0f6bcf | 460 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| 61525f2f | 461 | |
| 6d0f6bcf JCPV |
462 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 463 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
| 61525f2f | 464 | |
| 5a1aceb0 | 465 | #define CONFIG_ENV_IS_IN_FLASH |
| 61525f2f GL |
466 | /* |
| 467 | * The original LinkStation flash organisation uses | |
| 468 | * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader | |
| 469 | * We use the last sector of this area to store the environment | |
| 470 | * which leaves max. 384 kB for the U-Boot itself | |
| 471 | */ | |
| 0e8d1586 JCPV |
472 | #define CONFIG_ENV_ADDR 0xFFF60000 |
| 473 | #define CONFIG_ENV_SIZE 0x00010000 | |
| 474 | #define CONFIG_ENV_SECT_SIZE 0x00010000 | |
| 61525f2f GL |
475 | |
| 476 | /*----------------------------------------------------------------------- | |
| 477 | * Cache Configuration | |
| 478 | */ | |
| 6d0f6bcf | 479 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
| 61525f2f | 480 | #ifdef CONFIG_CMD_KGDB |
| 6d0f6bcf | 481 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 61525f2f GL |
482 | #endif |
| 483 | ||
| 484 | /*----------------------------------------------------------------------- | |
| 485 | * IDE/ATA definitions | |
| 486 | */ | |
| 487 | #undef CONFIG_IDE_LED /* No IDE LED */ | |
| 488 | #define CONFIG_IDE_RESET /* no reset for ide supported */ | |
| 489 | #define CONFIG_IDE_PREINIT /* check for units */ | |
| 490 | #define CONFIG_LBA48 /* 48 bit LBA supported */ | |
| 491 | ||
| 492 | #if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN) | |
| 6d0f6bcf JCPV |
493 | #define CONFIG_SYS_IDE_MAXBUS 1 /* Scan only 1 IDE bus */ |
| 494 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* Only 1 drive per IDE bus */ | |
| 61525f2f | 495 | #elif defined(CONFIG_HGTL) |
| 6d0f6bcf JCPV |
496 | #define CONFIG_SYS_IDE_MAXBUS 2 /* Max. 2 IDE busses */ |
| 497 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
| 61525f2f GL |
498 | #else |
| 499 | #error Config IDE: Unknown LinkStation type | |
| 500 | #endif | |
| 501 | ||
| 6d0f6bcf | 502 | #define CONFIG_SYS_ATA_BASE_ADDR 0 |
| 61525f2f | 503 | |
| 6d0f6bcf JCPV |
504 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* Offset for data I/O */ |
| 505 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* Offset for normal registers */ | |
| 506 | #define CONFIG_SYS_ATA_ALT_OFFSET 0 /* Offset for alternate registers */ | |
| 61525f2f GL |
507 | |
| 508 | /*----------------------------------------------------------------------- | |
| 509 | * Partitions and file system | |
| 510 | */ | |
| 511 | #define CONFIG_DOS_PARTITION | |
| 512 | ||
| 61525f2f | 513 | #endif /* __CONFIG_H */ |