[people/ms/u-boot.git] / include / configs / lp8x4x.h

/*
 * ICP DAS LP-8x4x configuration file
 *
 * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef	__CONFIG_H
#define	__CONFIG_H

/*
 * High Level Board Configuration Options
 */
#define	CONFIG_CPU_PXA27X			/* Marvell PXA270 CPU */
#define	MACH_TYPE_LP8X4X		4539	/* ICP DAS LP-8x4x */
#define	CONFIG_MACH_TYPE		MACH_TYPE_LP8X4X
#define	CONFIG_SYS_TEXT_BASE		0x00000000

#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
#define	CONFIG_ARCH_CPU_INIT
#define	CONFIG_BOOTCOMMAND		\
	"bootm 80000 - 240000;"

#define	CONFIG_BOOTARGS			\
	"console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
	"init=/sbin/init rootfstype=ext4 rootwait"

#define	CONFIG_TIMESTAMP
#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
#define	CONFIG_CMDLINE_TAG
#define	CONFIG_SETUP_MEMORY_TAGS
#define	CONFIG_LZMA			/* LZMA compression support */
#define	CONFIG_OF_LIBFDT

/*
 * Serial Console Configuration
 */
#define	CONFIG_PXA_SERIAL
#define	CONFIG_FFUART			1
#define	CONFIG_CONS_INDEX		3
#define	CONFIG_BAUDRATE			115200

/*
 * Bootloader Components Configuration
 */
#include <config_cmd_default.h>

#define	CONFIG_CMD_NET
#define	CONFIG_CMD_ENV
#undef	CONFIG_CMD_IMLS
#define	CONFIG_CMD_MMC
#define	CONFIG_CMD_USB
#undef	CONFIG_LCD
#undef	CONFIG_CMD_IDE

/*
 * Networking Configuration
 * chip on the ICPDAS LINPAC board
 */
#ifdef	CONFIG_CMD_NET
#define	CONFIG_CMD_PING
#define	CONFIG_CMD_DHCP

#define	CONFIG_DRIVER_DM9000		1
#define	CONFIG_DM9000_BASE		0x0C000000
#define	DM9000_IO			0x0C000000
#define	DM9000_DATA			0x0C004000
#define	DM9000_IO_2			0x0D000000
#define	DM9000_DATA_2			0x0D004000
#define	CONFIG_NET_RETRY_COUNT		10

#define	CONFIG_BOOTP_BOOTFILESIZE
#define	CONFIG_BOOTP_BOOTPATH
#define	CONFIG_BOOTP_GATEWAY
#define	CONFIG_BOOTP_HOSTNAME
#endif

/*
 * MMC Card Configuration
 */
#ifdef	CONFIG_CMD_MMC
#define	CONFIG_MMC
#define	CONFIG_GENERIC_MMC
#define	CONFIG_PXA_MMC_GENERIC
#define	CONFIG_CMD_FAT
#define	CONFIG_CMD_EXT2
#define	CONFIG_DOS_PARTITION
#endif

/*
 * KGDB
 */
#ifdef	CONFIG_CMD_KGDB
#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
#endif

/*
 * HUSH Shell Configuration
 */
#define	CONFIG_SYS_HUSH_PARSER		1

#define	CONFIG_SYS_LONGHELP
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT		"$ "
#else
#endif
#define	CONFIG_SYS_CBSIZE		256
#define	CONFIG_SYS_PBSIZE		\
	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS		16
#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define	CONFIG_SYS_DEVICE_NULLDEV	1
#define	CONFIG_CMDLINE_EDITING		1
#define	CONFIG_AUTO_COMPLETE		1

/*
 * DRAM Map
 */
#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define	PHYS_SDRAM_1_SIZE		0x08000000	/* 128 MB */

#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
#define	CONFIG_SYS_DRAM_SIZE		0x08000000	/* 128 MB DRAM */

#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

#define	CONFIG_SYS_LOAD_ADDR		0xa0008000
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
/* Use first 64kb bank of the internal SRAM */
#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000

/*
 * NOR FLASH
 */
#define	CONFIG_SYS_MONITOR_BASE		0x0
#define	CONFIG_SYS_MONITOR_LEN		0x40000
#define	CONFIG_ENV_ADDR			\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_ENV_SIZE			0x40000
#define	CONFIG_ENV_SECT_SIZE		0x40000

#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define	PHYS_FLASH_2			0x04000000	/* Flash Bank #2 */

#define	CONFIG_SYS_FLASH_CFI
#define	CONFIG_FLASH_CFI_DRIVER		1

#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
#define	CONFIG_SYS_MAX_FLASH_BANKS	2
#define	CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, PHYS_FLASH_2 }

#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ)

#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define	CONFIG_SYS_FLASH_PROTECTION		1

#define	CONFIG_ENV_IS_IN_FLASH		1

/*
 * GPIO settings
 */
#define	CONFIG_SYS_GPSR0_VAL	0x0808c014
#define	CONFIG_SYS_GPSR1_VAL	0x00cf0002
#define	CONFIG_SYS_GPSR2_VAL	0x0221c000
#define	CONFIG_SYS_GPSR3_VAL	0x00020000

#define	CONFIG_SYS_GPCR0_VAL	0x00000000
#define	CONFIG_SYS_GPCR1_VAL	0x0000ab80
#define	CONFIG_SYS_GPCR2_VAL	0x00100000
#define	CONFIG_SYS_GPCR3_VAL	0x0

#define	CONFIG_SYS_GPDR0_VAL	0xc0e9ddf4
#define	CONFIG_SYS_GPDR1_VAL	0xfcffab83
#define	CONFIG_SYS_GPDR2_VAL	0x02f1ffff
#define	CONFIG_SYS_GPDR3_VAL	0x00021b81

#define	CONFIG_SYS_GAFR0_L_VAL	0x80000000
#define	CONFIG_SYS_GAFR0_U_VAL	0xa5e54018
#define	CONFIG_SYS_GAFR1_L_VAL	0x999a955a
#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa5a00a
#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
#define	CONFIG_SYS_GAFR2_U_VAL	0x55f9a402
#define	CONFIG_SYS_GAFR3_L_VAL	0x540a950c
#define	CONFIG_SYS_GAFR3_U_VAL	0x00001599

#define	CONFIG_SYS_PSSR_VAL	0x32

/*
 * Clock settings
 */
#define	CONFIG_SYS_CKEN		0x005002c0
#define	CONFIG_SYS_CCCR		0x02000290
#define	CONFIG_SYS_CLKCFG	0x0000000b

/*
 * Memory settings
 */
#define	CONFIG_SYS_MSC0_VAL	0x2bd8aad2
#define	CONFIG_SYS_MSC1_VAL	0xb8c9b8dc
#define	CONFIG_SYS_MSC2_VAL	0xfff9b8c9
#define	CONFIG_SYS_FLYCNFG_VAL	0x00010001
#define	CONFIG_SYS_MDREFR_VAL	0x2093e018
#define	CONFIG_SYS_MDCNFG_VAL	0x890009d1
#define	CONFIG_SYS_MDMRS_VAL	0x00220022
#define	CONFIG_SYS_SXCNFG_VAL	0x40044004

/*
 * PCMCIA and CF Interfaces
 */
#define	CONFIG_SYS_MECR_VAL	0x00000001
#define	CONFIG_SYS_MCMEM0_VAL	0x0000c497
#define	CONFIG_SYS_MCMEM1_VAL	0x0000c497
#define	CONFIG_SYS_MCATT0_VAL	0x0000c497
#define	CONFIG_SYS_MCATT1_VAL	0x0000c497
#define	CONFIG_SYS_MCIO0_VAL	0x00008407
#define	CONFIG_SYS_MCIO1_VAL	0x00008407

/*
 * LCD
 */
#ifdef	CONFIG_LCD
#define	CONFIG_VOIPAC_LCD
#endif

/*
 * USB
 */
#ifdef	CONFIG_CMD_USB
#define	CONFIG_USB_OHCI_NEW
#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define	CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
#define	CONFIG_SYS_USB_OHCI_SLOT_NAME	"lp8x4x"
#define	CONFIG_USB_STORAGE
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
c3442c1e SY	1	/*
	2	* ICP DAS LP-8x4x configuration file
	3	*
	4	* Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
c3442c1e SY	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Board Configuration Options
	14	*/
	15	#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */
	16	#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */
	17	#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X
	18	#define CONFIG_SYS_TEXT_BASE 0x00000000
	19
	20	#define CONFIG_SYS_MALLOC_LEN (128*1024)
	21	#define CONFIG_ARCH_CPU_INIT
	22	#define CONFIG_BOOTCOMMAND \
7cd5441e	23	"bootm 80000 - 240000;"
c3442c1e SY	24
c3442c1e SY	25	#define CONFIG_BOOTARGS \
7cd5441e SI	26	"console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
7cd5441e SI	27	"init=/sbin/init rootfstype=ext4 rootwait"
c3442c1e SY	28
	29	#define CONFIG_TIMESTAMP
	30	#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
	31	#define CONFIG_CMDLINE_TAG
	32	#define CONFIG_SETUP_MEMORY_TAGS
	33	#define CONFIG_LZMA /* LZMA compression support */
7cd5441e	34	#define CONFIG_OF_LIBFDT
c3442c1e SY	35
	36	/*
	37	* Serial Console Configuration
	38	*/
	39	#define CONFIG_PXA_SERIAL
	40	#define CONFIG_FFUART 1
	41	#define CONFIG_CONS_INDEX 3
	42	#define CONFIG_BAUDRATE 115200
	43
	44	/*
	45	* Bootloader Components Configuration
	46	*/
	47	#include <config_cmd_default.h>
	48
	49	#define CONFIG_CMD_NET
	50	#define CONFIG_CMD_ENV
	51	#undef CONFIG_CMD_IMLS
	52	#define CONFIG_CMD_MMC
	53	#define CONFIG_CMD_USB
	54	#undef CONFIG_LCD
	55	#undef CONFIG_CMD_IDE
	56
	57	/*
	58	* Networking Configuration
	59	* chip on the ICPDAS LINPAC board
	60	*/
	61	#ifdef CONFIG_CMD_NET
	62	#define CONFIG_CMD_PING
	63	#define CONFIG_CMD_DHCP
	64
	65	#define CONFIG_DRIVER_DM9000 1
	66	#define CONFIG_DM9000_BASE 0x0C000000
	67	#define DM9000_IO 0x0C000000
	68	#define DM9000_DATA 0x0C004000
	69	#define DM9000_IO_2 0x0D000000
	70	#define DM9000_DATA_2 0x0D004000
	71	#define CONFIG_NET_RETRY_COUNT 10
	72
	73	#define CONFIG_BOOTP_BOOTFILESIZE
	74	#define CONFIG_BOOTP_BOOTPATH
	75	#define CONFIG_BOOTP_GATEWAY
	76	#define CONFIG_BOOTP_HOSTNAME
	77	#endif
	78
	79	/*
	80	* MMC Card Configuration
	81	*/
	82	#ifdef CONFIG_CMD_MMC
	83	#define CONFIG_MMC
	84	#define CONFIG_GENERIC_MMC
	85	#define CONFIG_PXA_MMC_GENERIC
	86	#define CONFIG_CMD_FAT
	87	#define CONFIG_CMD_EXT2
	88	#define CONFIG_DOS_PARTITION
	89	#endif
	90
	91	/*
	92	* KGDB
	93	*/
	94	#ifdef CONFIG_CMD_KGDB
	95	#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
c3442c1e SY	96	#endif
	97
	98	/*
	99	* HUSH Shell Configuration
	100	*/
	101	#define CONFIG_SYS_HUSH_PARSER 1
	102
7cd5441e	103	#define CONFIG_SYS_LONGHELP
c3442c1e SY	104	#ifdef CONFIG_SYS_HUSH_PARSER
	105	#define CONFIG_SYS_PROMPT "$ "
	106	#else
c3442c1e SY	107	#endif
	108	#define CONFIG_SYS_CBSIZE 256
	109	#define CONFIG_SYS_PBSIZE \
	110	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	111	#define CONFIG_SYS_MAXARGS 16
	112	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	113	#define CONFIG_SYS_DEVICE_NULLDEV 1
	114	#define CONFIG_CMDLINE_EDITING 1
	115	#define CONFIG_AUTO_COMPLETE 1
	116
c3442c1e SY	117	/*
	118	* DRAM Map
	119	*/
	120	#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
	121	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	122	#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
	123
	124	#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	125	#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
	126
	127	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	128	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	129
	130	#define CONFIG_SYS_LOAD_ADDR 0xa0008000
	131	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	132	/* Use first 64kb bank of the internal SRAM */
	133	#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
	134
	135	/*
	136	* NOR FLASH
	137	*/
	138	#define CONFIG_SYS_MONITOR_BASE 0x0
	139	#define CONFIG_SYS_MONITOR_LEN 0x40000
	140	#define CONFIG_ENV_ADDR \
	141	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	142	#define CONFIG_ENV_SIZE 0x40000
	143	#define CONFIG_ENV_SECT_SIZE 0x40000
	144
	145	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
bf92349b	146	#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
c3442c1e SY	147
	148	#define CONFIG_SYS_FLASH_CFI
	149	#define CONFIG_FLASH_CFI_DRIVER 1
	150
	151	#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
	152	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	153	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
	154
	155	#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
	156	#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
	157
	158	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	159	#define CONFIG_SYS_FLASH_PROTECTION 1
	160
	161	#define CONFIG_ENV_IS_IN_FLASH 1
	162
	163	/*
	164	* GPIO settings
	165	*/
	166	#define CONFIG_SYS_GPSR0_VAL 0x0808c014
	167	#define CONFIG_SYS_GPSR1_VAL 0x00cf0002
	168	#define CONFIG_SYS_GPSR2_VAL 0x0221c000
	169	#define CONFIG_SYS_GPSR3_VAL 0x00020000
	170
	171	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	172	#define CONFIG_SYS_GPCR1_VAL 0x0000ab80
	173	#define CONFIG_SYS_GPCR2_VAL 0x00100000
	174	#define CONFIG_SYS_GPCR3_VAL 0x0
	175
	176	#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4
	177	#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
	178	#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff
	179	#define CONFIG_SYS_GPDR3_VAL 0x00021b81
	180
	181	#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
	182	#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018
	183	#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a
	184	#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a
	185	#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
a3d6ca43	186	#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402
c3442c1e SY	187	#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
	188	#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
	189
	190	#define CONFIG_SYS_PSSR_VAL 0x32
	191
	192	/*
	193	* Clock settings
	194	*/
	195	#define CONFIG_SYS_CKEN 0x005002c0
	196	#define CONFIG_SYS_CCCR 0x02000290
	197	#define CONFIG_SYS_CLKCFG 0x0000000b
	198
	199	/*
	200	* Memory settings
	201	*/
	202	#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2
	203	#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc
	204	#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9
	205	#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
	206	#define CONFIG_SYS_MDREFR_VAL 0x2093e018
	207	#define CONFIG_SYS_MDCNFG_VAL 0x890009d1
	208	#define CONFIG_SYS_MDMRS_VAL 0x00220022
	209	#define CONFIG_SYS_SXCNFG_VAL 0x40044004
	210
	211	/*
	212	* PCMCIA and CF Interfaces
	213	*/
	214	#define CONFIG_SYS_MECR_VAL 0x00000001
	215	#define CONFIG_SYS_MCMEM0_VAL 0x0000c497
	216	#define CONFIG_SYS_MCMEM1_VAL 0x0000c497
	217	#define CONFIG_SYS_MCATT0_VAL 0x0000c497
	218	#define CONFIG_SYS_MCATT1_VAL 0x0000c497
	219	#define CONFIG_SYS_MCIO0_VAL 0x00008407
	220	#define CONFIG_SYS_MCIO1_VAL 0x00008407
	221
	222	/*
	223	* LCD
	224	*/
	225	#ifdef CONFIG_LCD
	226	#define CONFIG_VOIPAC_LCD
	227	#endif
	228
	229	/*
	230	* USB
	231	*/
	232	#ifdef CONFIG_CMD_USB
	233	#define CONFIG_USB_OHCI_NEW
c3442c1e SY	234	#define CONFIG_SYS_USB_OHCI_BOARD_INIT
	235	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
	236	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
	237	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x"
	238	#define CONFIG_USB_STORAGE
	239	#endif
	240
	241	#endif /* __CONFIG_H */