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550e3dc0 WH |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
550e3dc0 WH |
10 | #define CONFIG_LS102XA |
11 | ||
340848b1 WD |
12 | #define CONFIG_ARMV7_PSCI |
13 | ||
18fb0e3c | 14 | #define CONFIG_SYS_FSL_CLK |
550e3dc0 WH |
15 | |
16 | #define CONFIG_DISPLAY_CPUINFO | |
17 | #define CONFIG_DISPLAY_BOARDINFO | |
18 | ||
19 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
20 | #define CONFIG_BOARD_EARLY_INIT_F | |
21 | ||
41ba57d0 | 22 | #define CONFIG_DEEP_SLEEP |
23 | #if defined(CONFIG_DEEP_SLEEP) | |
24 | #define CONFIG_SILENT_CONSOLE | |
25 | #endif | |
26 | ||
550e3dc0 WH |
27 | /* |
28 | * Size of malloc() pool | |
29 | */ | |
30 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
31 | ||
32 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
33 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
34 | ||
35 | /* | |
36 | * Generic Timer Definitions | |
37 | */ | |
38 | #define GENERIC_TIMER_CLK 12500000 | |
39 | ||
40 | #ifndef __ASSEMBLY__ | |
41 | unsigned long get_board_sys_clk(void); | |
42 | unsigned long get_board_ddr_clk(void); | |
43 | #endif | |
44 | ||
d612f0ab AW |
45 | #ifdef CONFIG_QSPI_BOOT |
46 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
47 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
48 | #define CONFIG_QIXIS_I2C_ACCESS | |
49 | #else | |
550e3dc0 WH |
50 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
51 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
d612f0ab | 52 | #endif |
550e3dc0 | 53 | |
86949c2b AW |
54 | #ifdef CONFIG_RAMBOOT_PBL |
55 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg | |
56 | #endif | |
57 | ||
58 | #ifdef CONFIG_SD_BOOT | |
59 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | |
60 | #define CONFIG_SPL_FRAMEWORK | |
61 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
62 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
63 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
64 | #define CONFIG_SPL_ENV_SUPPORT | |
65 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
66 | #define CONFIG_SPL_I2C_SUPPORT | |
67 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
68 | #define CONFIG_SPL_SERIAL_SUPPORT | |
69 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
70 | #define CONFIG_SPL_MMC_SUPPORT | |
71 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 | |
7ee52af4 | 72 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 |
86949c2b AW |
73 | |
74 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
75 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
76 | #define CONFIG_SPL_STACK 0x1001d000 | |
77 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
78 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
79 | ||
41ba57d0 | 80 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
81 | CONFIG_SYS_MONITOR_LEN) | |
86949c2b AW |
82 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
83 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
84 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
7ee52af4 | 85 | #define CONFIG_SYS_MONITOR_LEN 0xc0000 |
86949c2b AW |
86 | #endif |
87 | ||
d612f0ab AW |
88 | #ifdef CONFIG_QSPI_BOOT |
89 | #define CONFIG_SYS_TEXT_BASE 0x40010000 | |
90 | #define CONFIG_SYS_NO_FLASH | |
91 | #endif | |
92 | ||
8ab967b6 AW |
93 | #ifdef CONFIG_NAND_BOOT |
94 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | |
95 | #define CONFIG_SPL_FRAMEWORK | |
96 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
97 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
98 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
99 | #define CONFIG_SPL_ENV_SUPPORT | |
100 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
101 | #define CONFIG_SPL_I2C_SUPPORT | |
102 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
103 | #define CONFIG_SPL_SERIAL_SUPPORT | |
104 | #define CONFIG_SPL_NAND_SUPPORT | |
105 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
106 | ||
107 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
108 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
109 | #define CONFIG_SPL_STACK 0x1001d000 | |
110 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
111 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
112 | ||
113 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) | |
114 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO | |
115 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
116 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
117 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
118 | ||
119 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
120 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
121 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
122 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
123 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
124 | #endif | |
125 | ||
550e3dc0 | 126 | #ifndef CONFIG_SYS_TEXT_BASE |
1c69a51c | 127 | #define CONFIG_SYS_TEXT_BASE 0x60100000 |
550e3dc0 WH |
128 | #endif |
129 | ||
130 | #define CONFIG_NR_DRAM_BANKS 1 | |
131 | ||
132 | #define CONFIG_DDR_SPD | |
133 | #define SPD_EEPROM_ADDRESS 0x51 | |
134 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
550e3dc0 WH |
135 | |
136 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ | |
c7eae7fc | 137 | #ifndef CONFIG_SYS_FSL_DDR4 |
550e3dc0 | 138 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ |
c7eae7fc YS |
139 | #define CONFIG_SYS_DDR_RAW_TIMING |
140 | #endif | |
550e3dc0 WH |
141 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
142 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
143 | ||
144 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
145 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
146 | ||
147 | #define CONFIG_DDR_ECC | |
148 | #ifdef CONFIG_DDR_ECC | |
149 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
150 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
151 | #endif | |
152 | ||
153 | #define CONFIG_SYS_HAS_SERDES | |
154 | ||
4ba4a095 | 155 | #define CONFIG_FSL_CAAM /* Enable CAAM */ |
63e75fd7 | 156 | |
4c59ab9c AW |
157 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
158 | !defined(CONFIG_QSPI_BOOT) | |
63e75fd7 ZQ |
159 | #define CONFIG_U_QE |
160 | #endif | |
161 | ||
550e3dc0 WH |
162 | /* |
163 | * IFC Definitions | |
164 | */ | |
d612f0ab | 165 | #ifndef CONFIG_QSPI_BOOT |
550e3dc0 WH |
166 | #define CONFIG_FSL_IFC |
167 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
168 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
169 | ||
170 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
171 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
172 | CSPR_PORT_SIZE_16 | \ | |
173 | CSPR_MSEL_NOR | \ | |
174 | CSPR_V) | |
175 | #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) | |
176 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
177 | + 0x8000000) | \ | |
178 | CSPR_PORT_SIZE_16 | \ | |
179 | CSPR_MSEL_NOR | \ | |
180 | CSPR_V) | |
181 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
182 | ||
183 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
184 | CSOR_NOR_TRHZ_80) | |
185 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
186 | FTIM0_NOR_TEADC(0x5) | \ | |
187 | FTIM0_NOR_TEAHC(0x5)) | |
188 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
189 | FTIM1_NOR_TRAD_NOR(0x1a) | \ | |
190 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
191 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
192 | FTIM2_NOR_TCH(0x4) | \ | |
193 | FTIM2_NOR_TWPH(0xe) | \ | |
194 | FTIM2_NOR_TWP(0x1c)) | |
195 | #define CONFIG_SYS_NOR_FTIM3 0 | |
196 | ||
197 | #define CONFIG_FLASH_CFI_DRIVER | |
198 | #define CONFIG_SYS_FLASH_CFI | |
199 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
200 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
201 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
202 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
272c5265 | 203 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
550e3dc0 WH |
204 | |
205 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
206 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
207 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
208 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
209 | ||
210 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
211 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ | |
212 | CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} | |
213 | ||
214 | /* | |
215 | * NAND Flash Definitions | |
216 | */ | |
217 | #define CONFIG_NAND_FSL_IFC | |
218 | ||
219 | #define CONFIG_SYS_NAND_BASE 0x7e800000 | |
220 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
221 | ||
222 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
223 | ||
224 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
225 | | CSPR_PORT_SIZE_8 \ | |
226 | | CSPR_MSEL_NAND \ | |
227 | | CSPR_V) | |
228 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
229 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
230 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
231 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
232 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ | |
233 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
234 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | |
235 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ | |
236 | ||
237 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
238 | ||
239 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ | |
240 | FTIM0_NAND_TWP(0x18) | \ | |
241 | FTIM0_NAND_TWCHT(0x7) | \ | |
242 | FTIM0_NAND_TWH(0xa)) | |
243 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
244 | FTIM1_NAND_TWBE(0x39) | \ | |
245 | FTIM1_NAND_TRR(0xe) | \ | |
246 | FTIM1_NAND_TRP(0x18)) | |
247 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ | |
248 | FTIM2_NAND_TREH(0xa) | \ | |
249 | FTIM2_NAND_TWHRE(0x1e)) | |
250 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
251 | ||
252 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
253 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
550e3dc0 WH |
254 | #define CONFIG_CMD_NAND |
255 | ||
256 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
d612f0ab | 257 | #endif |
550e3dc0 WH |
258 | |
259 | /* | |
260 | * QIXIS Definitions | |
261 | */ | |
262 | #define CONFIG_FSL_QIXIS | |
263 | ||
264 | #ifdef CONFIG_FSL_QIXIS | |
265 | #define QIXIS_BASE 0x7fb00000 | |
266 | #define QIXIS_BASE_PHYS QIXIS_BASE | |
267 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
268 | #define QIXIS_LBMAP_SWITCH 6 | |
269 | #define QIXIS_LBMAP_MASK 0x0f | |
270 | #define QIXIS_LBMAP_SHIFT 0 | |
271 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
272 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
273 | #define QIXIS_RST_CTL_RESET 0x44 | |
274 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
275 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
276 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
277 | ||
278 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
279 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ | |
280 | CSPR_PORT_SIZE_8 | \ | |
281 | CSPR_MSEL_GPCM | \ | |
282 | CSPR_V) | |
283 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
284 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
285 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
286 | CSOR_NOR_TRHZ_80) | |
287 | ||
288 | /* | |
289 | * QIXIS Timing parameters for IFC GPCM | |
290 | */ | |
291 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ | |
292 | FTIM0_GPCM_TEADC(0xe) | \ | |
293 | FTIM0_GPCM_TEAHC(0xe)) | |
294 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ | |
295 | FTIM1_GPCM_TRAD(0x1f)) | |
296 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ | |
297 | FTIM2_GPCM_TCH(0xe) | \ | |
298 | FTIM2_GPCM_TWP(0xf0)) | |
299 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
300 | #endif | |
301 | ||
8ab967b6 AW |
302 | #if defined(CONFIG_NAND_BOOT) |
303 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
304 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
305 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
306 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
307 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
308 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
309 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
310 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
311 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
312 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
313 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
314 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
315 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
316 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
317 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
318 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
319 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
320 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
321 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
322 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
323 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
324 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
325 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
326 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
327 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
328 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
329 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
330 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
331 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
332 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
333 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
334 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
335 | #else | |
550e3dc0 WH |
336 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
337 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
338 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
339 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
340 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
341 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
342 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
343 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
344 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
345 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
346 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
347 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
348 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
349 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
350 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
351 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
352 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
353 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
354 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
355 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
356 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
357 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
358 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
359 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
360 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
361 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
362 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
363 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
364 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
365 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
366 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
367 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
8ab967b6 | 368 | #endif |
550e3dc0 WH |
369 | |
370 | /* | |
371 | * Serial Port | |
372 | */ | |
8fc2121a | 373 | #ifdef CONFIG_LPUART |
8fc2121a AW |
374 | #define CONFIG_LPUART_32B_REG |
375 | #else | |
550e3dc0 | 376 | #define CONFIG_CONS_INDEX 1 |
550e3dc0 WH |
377 | #define CONFIG_SYS_NS16550_SERIAL |
378 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
379 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
8fc2121a | 380 | #endif |
550e3dc0 WH |
381 | |
382 | #define CONFIG_BAUDRATE 115200 | |
383 | ||
384 | /* | |
385 | * I2C | |
386 | */ | |
387 | #define CONFIG_CMD_I2C | |
388 | #define CONFIG_SYS_I2C | |
389 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
390 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
391 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 392 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
550e3dc0 WH |
393 | |
394 | /* | |
395 | * I2C bus multiplexer | |
396 | */ | |
397 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
398 | #define I2C_MUX_CH_DEFAULT 0x8 | |
dd04832d | 399 | #define I2C_MUX_CH_CH7301 0xC |
550e3dc0 WH |
400 | |
401 | /* | |
402 | * MMC | |
403 | */ | |
404 | #define CONFIG_MMC | |
405 | #define CONFIG_CMD_MMC | |
406 | #define CONFIG_FSL_ESDHC | |
407 | #define CONFIG_GENERIC_MMC | |
408 | ||
8251ed23 AW |
409 | #define CONFIG_CMD_FAT |
410 | #define CONFIG_DOS_PARTITION | |
411 | ||
e5493d4e | 412 | /* SPI */ |
d612f0ab | 413 | #ifdef CONFIG_QSPI_BOOT |
e5493d4e | 414 | /* QSPI */ |
d612f0ab AW |
415 | #define QSPI0_AMBA_BASE 0x40000000 |
416 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
417 | #define FSL_QSPI_FLASH_NUM 2 | |
418 | ||
e5493d4e | 419 | /* DSPI */ |
e5493d4e HW |
420 | |
421 | /* DM SPI */ | |
422 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
d612f0ab | 423 | #define CONFIG_CMD_SF |
e5493d4e | 424 | #define CONFIG_DM_SPI_FLASH |
6812484a | 425 | #define CONFIG_SPI_FLASH_DATAFLASH |
e5493d4e | 426 | #endif |
d612f0ab AW |
427 | #endif |
428 | ||
8776cb20 NB |
429 | /* |
430 | * USB | |
431 | */ | |
081a1b73 RM |
432 | /* EHCI Support - disbaled by default */ |
433 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
8776cb20 NB |
434 | |
435 | #ifdef CONFIG_HAS_FSL_DR_USB | |
436 | #define CONFIG_USB_EHCI | |
081a1b73 RM |
437 | #define CONFIG_USB_EHCI_FSL |
438 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
439 | #endif | |
8776cb20 | 440 | |
081a1b73 RM |
441 | /*XHCI Support - enabled by default*/ |
442 | #define CONFIG_HAS_FSL_XHCI_USB | |
443 | ||
444 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
445 | #define CONFIG_USB_XHCI_FSL | |
446 | #define CONFIG_USB_XHCI_DWC3 | |
447 | #define CONFIG_USB_XHCI | |
448 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
449 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
450 | #endif | |
451 | ||
452 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) | |
8776cb20 NB |
453 | #define CONFIG_CMD_USB |
454 | #define CONFIG_USB_STORAGE | |
8776cb20 NB |
455 | #define CONFIG_CMD_EXT2 |
456 | #endif | |
8776cb20 | 457 | |
dd04832d XL |
458 | /* |
459 | * Video | |
460 | */ | |
461 | #define CONFIG_FSL_DCU_FB | |
462 | ||
463 | #ifdef CONFIG_FSL_DCU_FB | |
464 | #define CONFIG_VIDEO | |
465 | #define CONFIG_CMD_BMP | |
466 | #define CONFIG_CFB_CONSOLE | |
467 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
468 | #define CONFIG_VIDEO_LOGO | |
469 | #define CONFIG_VIDEO_BMP_LOGO | |
470 | ||
471 | #define CONFIG_FSL_DIU_CH7301 | |
472 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 | |
473 | #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 | |
474 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
475 | #endif | |
476 | ||
550e3dc0 WH |
477 | /* |
478 | * eTSEC | |
479 | */ | |
480 | #define CONFIG_TSEC_ENET | |
481 | ||
482 | #ifdef CONFIG_TSEC_ENET | |
483 | #define CONFIG_MII | |
484 | #define CONFIG_MII_DEFAULT_TSEC 3 | |
485 | #define CONFIG_TSEC1 1 | |
486 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
487 | #define CONFIG_TSEC2 1 | |
488 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
489 | #define CONFIG_TSEC3 1 | |
490 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
491 | ||
492 | #define TSEC1_PHY_ADDR 1 | |
493 | #define TSEC2_PHY_ADDR 2 | |
494 | #define TSEC3_PHY_ADDR 3 | |
495 | ||
496 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
497 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
498 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
499 | ||
500 | #define TSEC1_PHYIDX 0 | |
501 | #define TSEC2_PHYIDX 0 | |
502 | #define TSEC3_PHYIDX 0 | |
503 | ||
504 | #define CONFIG_ETHPRIME "eTSEC1" | |
505 | ||
506 | #define CONFIG_PHY_GIGE | |
507 | #define CONFIG_PHYLIB | |
508 | #define CONFIG_PHY_REALTEK | |
509 | ||
510 | #define CONFIG_HAS_ETH0 | |
511 | #define CONFIG_HAS_ETH1 | |
512 | #define CONFIG_HAS_ETH2 | |
513 | ||
514 | #define CONFIG_FSL_SGMII_RISER 1 | |
515 | #define SGMII_RISER_PHY_OFFSET 0x1b | |
516 | ||
517 | #ifdef CONFIG_FSL_SGMII_RISER | |
518 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
519 | #endif | |
520 | ||
521 | #endif | |
da419027 ML |
522 | |
523 | /* PCIe */ | |
524 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
525 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
526 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
527 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
528 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" | |
529 | ||
180b8688 ML |
530 | #define CONFIG_SYS_PCI_64BIT |
531 | ||
532 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
533 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
534 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
535 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
536 | ||
537 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
538 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
539 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
540 | ||
541 | #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 | |
542 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 | |
543 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ | |
544 | ||
545 | #ifdef CONFIG_PCI | |
180b8688 | 546 | #define CONFIG_PCI_PNP |
180b8688 ML |
547 | #define CONFIG_PCI_SCAN_SHOW |
548 | #define CONFIG_CMD_PCI | |
180b8688 ML |
549 | #endif |
550 | ||
550e3dc0 WH |
551 | #define CONFIG_CMD_PING |
552 | #define CONFIG_CMD_DHCP | |
553 | #define CONFIG_CMD_MII | |
550e3dc0 WH |
554 | |
555 | #define CONFIG_CMDLINE_TAG | |
556 | #define CONFIG_CMDLINE_EDITING | |
86949c2b | 557 | |
1a2826f6 XL |
558 | #define CONFIG_ARMV7_NONSEC |
559 | #define CONFIG_ARMV7_VIRT | |
560 | #define CONFIG_PEN_ADDR_BIG_ENDIAN | |
435acd83 | 561 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
1a2826f6 XL |
562 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
563 | #define CONFIG_TIMER_CLK_FREQ 12500000 | |
1a2826f6 | 564 | |
550e3dc0 | 565 | #define CONFIG_HWCONFIG |
03c22449 ZZ |
566 | #define HWCONFIG_BUFFER_SIZE 256 |
567 | ||
568 | #define CONFIG_FSL_DEVICE_DISABLE | |
550e3dc0 WH |
569 | |
570 | #define CONFIG_BOOTDELAY 3 | |
571 | ||
713bf94f | 572 | #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 |
63e75fd7 | 573 | |
8fc2121a AW |
574 | #ifdef CONFIG_LPUART |
575 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
576 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ | |
99fe4541 AW |
577 | "fdt_high=0xffffffff\0" \ |
578 | "initrd_high=0xffffffff\0" \ | |
8fc2121a AW |
579 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" |
580 | #else | |
550e3dc0 WH |
581 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
582 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
99fe4541 AW |
583 | "fdt_high=0xffffffff\0" \ |
584 | "initrd_high=0xffffffff\0" \ | |
550e3dc0 | 585 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" |
8fc2121a | 586 | #endif |
550e3dc0 WH |
587 | |
588 | /* | |
589 | * Miscellaneous configurable options | |
590 | */ | |
591 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
592 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
593 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
550e3dc0 WH |
594 | #define CONFIG_AUTO_COMPLETE |
595 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
596 | #define CONFIG_SYS_PBSIZE \ | |
597 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
598 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
599 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
600 | ||
550e3dc0 WH |
601 | #define CONFIG_CMD_GREPENV |
602 | #define CONFIG_CMD_MEMINFO | |
603 | #define CONFIG_CMD_MEMTEST | |
604 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
605 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
606 | ||
607 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
550e3dc0 | 608 | |
660673af XL |
609 | #define CONFIG_LS102XA_STREAM_ID |
610 | ||
550e3dc0 WH |
611 | /* |
612 | * Stack sizes | |
613 | * The stack sizes are set up in start.S using the settings below | |
614 | */ | |
615 | #define CONFIG_STACKSIZE (30 * 1024) | |
616 | ||
617 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
618 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
619 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
620 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
621 | ||
86949c2b AW |
622 | #ifdef CONFIG_SPL_BUILD |
623 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
624 | #else | |
550e3dc0 | 625 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
86949c2b | 626 | #endif |
550e3dc0 WH |
627 | |
628 | /* | |
629 | * Environment | |
630 | */ | |
631 | #define CONFIG_ENV_OVERWRITE | |
632 | ||
86949c2b AW |
633 | #if defined(CONFIG_SD_BOOT) |
634 | #define CONFIG_ENV_OFFSET 0x100000 | |
635 | #define CONFIG_ENV_IS_IN_MMC | |
636 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
637 | #define CONFIG_ENV_SIZE 0x2000 | |
d612f0ab AW |
638 | #elif defined(CONFIG_QSPI_BOOT) |
639 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
640 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
641 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
642 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
8ab967b6 AW |
643 | #elif defined(CONFIG_NAND_BOOT) |
644 | #define CONFIG_ENV_IS_IN_NAND | |
645 | #define CONFIG_ENV_SIZE 0x2000 | |
646 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
86949c2b | 647 | #else |
550e3dc0 WH |
648 | #define CONFIG_ENV_IS_IN_FLASH |
649 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
650 | #define CONFIG_ENV_SIZE 0x2000 | |
651 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
86949c2b | 652 | #endif |
550e3dc0 WH |
653 | |
654 | #define CONFIG_OF_LIBFDT | |
655 | #define CONFIG_OF_BOARD_SETUP | |
6b6db0d5 | 656 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
550e3dc0 WH |
657 | #define CONFIG_CMD_BOOTZ |
658 | ||
4ba4a095 RG |
659 | #define CONFIG_MISC_INIT_R |
660 | ||
661 | /* Hash command with SHA acceleration supported in hardware */ | |
662 | #define CONFIG_CMD_HASH | |
663 | #define CONFIG_SHA_HW_ACCEL | |
664 | ||
ba474020 RG |
665 | #ifdef CONFIG_SECURE_BOOT |
666 | #define CONFIG_CMD_BLOB | |
98cb0efd | 667 | #include <asm/fsl_secure_boot.h> |
ba474020 RG |
668 | #endif |
669 | ||
550e3dc0 | 670 | #endif |