[thirdparty/u-boot.git] / include / configs / ls1021aqds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2019 NXP
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_DEEP_SLEEP

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
#endif

#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0xc0000
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000

#define CONFIG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0x80000
#endif

#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR	1

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1a) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0xe) | \
					FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_SYS_WRITE_SWAPPED_DATA

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}

/*
 * NAND Flash Definitions
 */

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#endif

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_PWR_CTL			0x21
#define QIXIS_PWR_CTL_POWEROFF		0x80
#define QIXIS_RST_CTL_RESET		0x44
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_CTL_SYS			0x5
#define QIXIS_CTL_SYS_EVTSW_MASK	0x0c
#define QIXIS_CTL_SYS_EVTSW_IRQ		0x04
#define QIXIS_RST_FORCE_3		0x45
#define QIXIS_RST_FORCE_3_PCIESLOT1	0x80
#define QIXIS_PWR_CTL2			0x21
#define QIXIS_PWR_CTL2_PCTL		0x2

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/*
 * QIXIS Timing parameters for IFC GPCM
 */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xe) | \
					FTIM0_GPCM_TEADC(0xe) | \
					FTIM0_GPCM_TEAHC(0xe))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xe) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xe) | \
					FTIM2_GPCM_TCH(0xe) | \
					FTIM2_GPCM_TWP(0xf0))
#define CONFIG_SYS_FPGA_FTIM3		0x0
#endif

#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#endif

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */

/* GPIO */

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH_CH7301		0xC

/*
 * MMC
 */

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM	0
#define CONFIG_SYS_I2C_QIXIS_ADDR	0x66
#define CONFIG_SYS_I2C_DVI_ADDR		0x75
#endif

/*
 * eTSEC
 */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII_DEFAULT_TSEC		3
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			1
#define TSEC2_PHY_ADDR			2
#define TSEC3_PHY_ADDR			3

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_FSL_SGMII_RISER		1
#define SGMII_RISER_PHY_OFFSET		0x1b

#ifdef CONFIG_FSL_SGMII_RISER
#define CONFIG_SYS_TBIPA_VALUE		8
#endif

#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

/*
 * Environment
 */

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
550e3dc0 WH	2	/*
550e3dc0 WH	3	* Copyright 2014 Freescale Semiconductor, Inc.
9ebde884	4	* Copyright 2019 NXP
550e3dc0 WH	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
41ba57d0	10	#define CONFIG_DEEP_SLEEP
41ba57d0	11
550e3dc0 WH	12	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	13	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	14
70097027	15	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
d612f0ab	16	#define CONFIG_QIXIS_I2C_ACCESS
d612f0ab	17	#endif
550e3dc0	18
86949c2b	19	#ifdef CONFIG_SD_BOOT
86949c2b AW	20	#define CONFIG_SPL_MAX_SIZE 0x1a000
	21	#define CONFIG_SPL_STACK 0x1001d000
	22	#define CONFIG_SPL_PAD_TO 0x1c000
86949c2b	23
41ba57d0	24	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
41ba57d0	25	CONFIG_SYS_MONITOR_LEN)
86949c2b AW	26	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	27	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	28	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
7ee52af4	29	#define CONFIG_SYS_MONITOR_LEN 0xc0000
86949c2b AW	30	#endif
86949c2b AW	31
8ab967b6	32	#ifdef CONFIG_NAND_BOOT
8ab967b6 AW	33	#define CONFIG_SPL_MAX_SIZE 0x1a000
	34	#define CONFIG_SPL_STACK 0x1001d000
	35	#define CONFIG_SPL_PAD_TO 0x1c000
8ab967b6 AW	36
8ab967b6 AW	37	#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
8ab967b6 AW	38	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	39	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	40
	41	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	42	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	43	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	44	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	45	#define CONFIG_SYS_MONITOR_LEN 0x80000
	46	#endif
	47
550e3dc0 WH	48	#define SPD_EEPROM_ADDRESS 0x51
550e3dc0 WH	49	#define CONFIG_SYS_SPD_BUS_NUM 0
550e3dc0	50
c7eae7fc	51	#ifndef CONFIG_SYS_FSL_DDR4
c7eae7fc YS	52	#define CONFIG_SYS_DDR_RAW_TIMING
c7eae7fc YS	53	#endif
550e3dc0	54	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
550e3dc0 WH	55
	56	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	57	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	58
550e3dc0	59	#ifdef CONFIG_DDR_ECC
550e3dc0 WH	60	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	61	#endif
	62
550e3dc0 WH	63	/*
	64	* IFC Definitions
	65	*/
70097027	66	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
550e3dc0 WH	67	#define CONFIG_SYS_FLASH_BASE 0x60000000
	68	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	69
	70	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	71	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	72	CSPR_PORT_SIZE_16 \| \
	73	CSPR_MSEL_NOR \| \
	74	CSPR_V)
	75	#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
	76	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	77	+ 0x8000000) \| \
	78	CSPR_PORT_SIZE_16 \| \
	79	CSPR_MSEL_NOR \| \
	80	CSPR_V)
	81	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	82
	83	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	84	CSOR_NOR_TRHZ_80)
	85	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	86	FTIM0_NOR_TEADC(0x5) \| \
	87	FTIM0_NOR_TEAHC(0x5))
	88	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	89	FTIM1_NOR_TRAD_NOR(0x1a) \| \
	90	FTIM1_NOR_TSEQRAD_NOR(0x13))
	91	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	92	FTIM2_NOR_TCH(0x4) \| \
	93	FTIM2_NOR_TWPH(0xe) \| \
	94	FTIM2_NOR_TWP(0x1c))
	95	#define CONFIG_SYS_NOR_FTIM3 0
	96
550e3dc0 WH	97	#define CONFIG_SYS_FLASH_QUIET_TEST
550e3dc0 WH	98	#define CONFIG_FLASH_SHOW_PROGRESS 45
272c5265	99	#define CONFIG_SYS_WRITE_SWAPPED_DATA
550e3dc0	100
550e3dc0 WH	101	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	102	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	103	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	104
	105	#define CONFIG_SYS_FLASH_EMPTY_INFO
	106	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
	107	CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
	108
	109	/*
	110	* NAND Flash Definitions
	111	*/
550e3dc0 WH	112
	113	#define CONFIG_SYS_NAND_BASE 0x7e800000
	114	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	115
	116	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	117
	118	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	119	\| CSPR_PORT_SIZE_8 \
	120	\| CSPR_MSEL_NAND \
	121	\| CSPR_V)
	122	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	123	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	124	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	125	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	126	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	127	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	128	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	129	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	130
550e3dc0 WH	131	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	132	FTIM0_NAND_TWP(0x18) \| \
	133	FTIM0_NAND_TWCHT(0x7) \| \
	134	FTIM0_NAND_TWH(0xa))
	135	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	136	FTIM1_NAND_TWBE(0x39) \| \
	137	FTIM1_NAND_TRR(0xe) \| \
	138	FTIM1_NAND_TRP(0x18))
	139	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	140	FTIM2_NAND_TREH(0xa) \| \
	141	FTIM2_NAND_TWHRE(0x1e))
	142	#define CONFIG_SYS_NAND_FTIM3 0x0
	143
	144	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	145	#define CONFIG_SYS_MAX_NAND_DEVICE 1
d612f0ab	146	#endif
550e3dc0 WH	147
	148	/*
	149	* QIXIS Definitions
	150	*/
	151	#define CONFIG_FSL_QIXIS
	152
	153	#ifdef CONFIG_FSL_QIXIS
	154	#define QIXIS_BASE 0x7fb00000
	155	#define QIXIS_BASE_PHYS QIXIS_BASE
	156	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	157	#define QIXIS_LBMAP_SWITCH 6
	158	#define QIXIS_LBMAP_MASK 0x0f
	159	#define QIXIS_LBMAP_SHIFT 0
	160	#define QIXIS_LBMAP_DFLTBANK 0x00
	161	#define QIXIS_LBMAP_ALTBANK 0x04
aeb901f2 HZ	162	#define QIXIS_PWR_CTL 0x21
aeb901f2 HZ	163	#define QIXIS_PWR_CTL_POWEROFF 0x80
550e3dc0 WH	164	#define QIXIS_RST_CTL_RESET 0x44
	165	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	166	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	167	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
349cfc97 HZ	168	#define QIXIS_CTL_SYS 0x5
	169	#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
	170	#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
	171	#define QIXIS_RST_FORCE_3 0x45
	172	#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
	173	#define QIXIS_PWR_CTL2 0x21
	174	#define QIXIS_PWR_CTL2_PCTL 0x2
550e3dc0 WH	175
	176	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	177	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
	178	CSPR_PORT_SIZE_8 \| \
	179	CSPR_MSEL_GPCM \| \
	180	CSPR_V)
	181	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	182	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	183	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	184	CSOR_NOR_TRHZ_80)
	185
	186	/*
	187	* QIXIS Timing parameters for IFC GPCM
	188	*/
	189	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) \| \
	190	FTIM0_GPCM_TEADC(0xe) \| \
	191	FTIM0_GPCM_TEAHC(0xe))
	192	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) \| \
	193	FTIM1_GPCM_TRAD(0x1f))
	194	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) \| \
	195	FTIM2_GPCM_TCH(0xe) \| \
	196	FTIM2_GPCM_TWP(0xf0))
	197	#define CONFIG_SYS_FPGA_FTIM3 0x0
	198	#endif
	199
8ab967b6 AW	200	#if defined(CONFIG_NAND_BOOT)
	201	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	202	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	203	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	204	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	205	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	206	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	207	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	208	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	209	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	210	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	211	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	212	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	213	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	214	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	215	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	216	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	217	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
	218	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
	219	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	220	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	221	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	222	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	223	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	224	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	225	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	226	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	227	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	228	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	229	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	230	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	231	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	232	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
	233	#else
550e3dc0 WH	234	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	235	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	236	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	237	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	238	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	239	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	240	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	241	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	242	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
	243	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
	244	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	245	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	246	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	247	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	248	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	249	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	250	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	251	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	252	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	253	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	254	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	255	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	256	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	257	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	258	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	259	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	260	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	261	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	262	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	263	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	264	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	265	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
8ab967b6	266	#endif
550e3dc0 WH	267
	268	/*
	269	* Serial Port
	270	*/
8fc2121a	271	#ifdef CONFIG_LPUART
8fc2121a AW	272	#define CONFIG_LPUART_32B_REG
8fc2121a AW	273	#else
550e3dc0	274	#define CONFIG_SYS_NS16550_SERIAL
d83b47b7	275	#ifndef CONFIG_DM_SERIAL
550e3dc0	276	#define CONFIG_SYS_NS16550_REG_SIZE 1
d83b47b7	277	#endif
550e3dc0	278	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
8fc2121a	279	#endif
550e3dc0	280
550e3dc0 WH	281	/*
	282	* I2C
	283	*/
550e3dc0	284
d58ea638	285	/* GPIO */
d58ea638	286
73dc91f9	287	/* EEPROM */
73dc91f9 JG	288	#define CONFIG_SYS_I2C_EEPROM_NXID
73dc91f9 JG	289	#define CONFIG_SYS_EEPROM_BUS_NUM 0
73dc91f9	290
550e3dc0 WH	291	/*
	292	* I2C bus multiplexer
	293	*/
	294	#define I2C_MUX_PCA_ADDR_PRI 0x77
	295	#define I2C_MUX_CH_DEFAULT 0x8
dd04832d	296	#define I2C_MUX_CH_CH7301 0xC
550e3dc0 WH	297
	298	/*
	299	* MMC
	300	*/
550e3dc0	301
dd04832d XL	302	/*
	303	* Video
	304	*/
b215fb3f	305	#ifdef CONFIG_VIDEO_FSL_DCU_FB
dd04832d XL	306	#define CONFIG_VIDEO_BMP_LOGO
	307
	308	#define CONFIG_FSL_DIU_CH7301
	309	#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
	310	#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
	311	#define CONFIG_SYS_I2C_DVI_ADDR 0x75
	312	#endif
	313
550e3dc0 WH	314	/*
	315	* eTSEC
	316	*/
550e3dc0 WH	317
550e3dc0 WH	318	#ifdef CONFIG_TSEC_ENET
550e3dc0 WH	319	#define CONFIG_MII_DEFAULT_TSEC 3
	320	#define CONFIG_TSEC1 1
	321	#define CONFIG_TSEC1_NAME "eTSEC1"
	322	#define CONFIG_TSEC2 1
	323	#define CONFIG_TSEC2_NAME "eTSEC2"
	324	#define CONFIG_TSEC3 1
	325	#define CONFIG_TSEC3_NAME "eTSEC3"
	326
	327	#define TSEC1_PHY_ADDR 1
	328	#define TSEC2_PHY_ADDR 2
	329	#define TSEC3_PHY_ADDR 3
	330
	331	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	332	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	333	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	334
	335	#define TSEC1_PHYIDX 0
	336	#define TSEC2_PHYIDX 0
	337	#define TSEC3_PHYIDX 0
	338
550e3dc0 WH	339	#define CONFIG_FSL_SGMII_RISER 1
	340	#define SGMII_RISER_PHY_OFFSET 0x1b
	341
	342	#ifdef CONFIG_FSL_SGMII_RISER
	343	#define CONFIG_SYS_TBIPA_VALUE 8
	344	#endif
	345
	346	#endif
da419027 ML	347
da419027 ML	348	/* PCIe */
b38eaec5 RD	349	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	350	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	351
180b8688	352	#ifdef CONFIG_PCI
180b8688	353	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	354	#endif
180b8688 ML	355
1a2826f6	356	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	357	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	358	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	359	#define COUNTER_FREQUENCY 12500000
1a2826f6	360
550e3dc0	361	#define CONFIG_HWCONFIG
03c22449 ZZ	362	#define HWCONFIG_BUFFER_SIZE 256
	363
	364	#define CONFIG_FSL_DEVICE_DISABLE
550e3dc0	365
8fc2121a AW	366	#ifdef CONFIG_LPUART
	367	#define CONFIG_EXTRA_ENV_SETTINGS \
	368	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
99fe4541	369	"initrd_high=0xffffffff\0" \
8fc2121a AW	370	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
8fc2121a AW	371	#else
550e3dc0 WH	372	#define CONFIG_EXTRA_ENV_SETTINGS \
550e3dc0 WH	373	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
99fe4541	374	"initrd_high=0xffffffff\0" \
550e3dc0	375	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
8fc2121a	376	#endif
550e3dc0 WH	377
	378	/*
	379	* Miscellaneous configurable options
	380	*/
c463eeb4	381	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
550e3dc0	382
660673af XL	383	#define CONFIG_LS102XA_STREAM_ID
660673af XL	384
550e3dc0 WH	385	#define CONFIG_SYS_INIT_SP_OFFSET \
	386	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	387	#define CONFIG_SYS_INIT_SP_ADDR \
	388	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	389
86949c2b AW	390	#ifdef CONFIG_SPL_BUILD
	391	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	392	#else
550e3dc0	393	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
86949c2b	394	#endif
550e3dc0 WH	395
	396	/*
	397	* Environment
	398	*/
550e3dc0	399
ef6c55a2	400	#include <asm/fsl_secure_boot.h>
cc7b8b9a	401	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	402
550e3dc0	403	#endif