[thirdparty/u-boot.git] / include / configs / ls1021aqds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2019 NXP
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_DEEP_SLEEP

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000
#define CONFIG_QIXIS_I2C_ACCESS
#else
#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
#endif

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021aqds/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
#endif

#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0xc0000
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg

#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000

#define CONFIG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0x80000
#endif

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1a) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0xe) | \
					FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#endif

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_PWR_CTL			0x21
#define QIXIS_PWR_CTL_POWEROFF		0x80
#define QIXIS_RST_CTL_RESET		0x44
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_CTL_SYS			0x5
#define QIXIS_CTL_SYS_EVTSW_MASK	0x0c
#define QIXIS_CTL_SYS_EVTSW_IRQ		0x04
#define QIXIS_RST_FORCE_3		0x45
#define QIXIS_RST_FORCE_3_PCIESLOT1	0x80
#define QIXIS_PWR_CTL2			0x21
#define QIXIS_PWR_CTL2_PCTL		0x2

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/*
 * QIXIS Timing parameters for IFC GPCM
 */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xe) | \
					FTIM0_GPCM_TEADC(0xe) | \
					FTIM0_GPCM_TEAHC(0xe))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xe) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xe) | \
					FTIM2_GPCM_TCH(0xe) | \
					FTIM2_GPCM_TWP(0xf0))
#define CONFIG_SYS_FPGA_FTIM3		0x0
#endif

#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#endif

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH_CH7301		0xC

/*
 * MMC
 */

/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/* DSPI */

/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_DATAFLASH
#endif
#endif

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM	0
#define CONFIG_SYS_I2C_QIXIS_ADDR	0x66
#define CONFIG_SYS_I2C_DVI_ADDR		0x75
#endif

/*
 * eTSEC
 */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII_DEFAULT_TSEC		3
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			1
#define TSEC2_PHY_ADDR			2
#define TSEC3_PHY_ADDR			3

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2

#define CONFIG_FSL_SGMII_RISER		1
#define SGMII_RISER_PHY_OFFSET		0x1b

#ifdef CONFIG_FSL_SGMII_RISER
#define CONFIG_SYS_TBIPA_VALUE		8
#endif

#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

#define CONFIG_CMDLINE_TAG

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE


#define CONFIG_SYS_QE_FW_ADDR     0x60940000

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"initrd_high=0xffffffff\0"      \
	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV		0
#endif

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
550e3dc0 WH	2	/*
550e3dc0 WH	3	* Copyright 2014 Freescale Semiconductor, Inc.
9ebde884	4	* Copyright 2019 NXP
550e3dc0 WH	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
aeb901f2	10	#define CONFIG_ARMV7_PSCI_1_0
340848b1	11
3288628a HZ	12	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	13
18fb0e3c	14	#define CONFIG_SYS_FSL_CLK
550e3dc0	15
550e3dc0	16	#define CONFIG_SKIP_LOWLEVEL_INIT
550e3dc0	17
41ba57d0	18	#define CONFIG_DEEP_SLEEP
41ba57d0	19
550e3dc0 WH	20	/*
	21	* Size of malloc() pool
	22	*/
	23	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	24
	25	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	26	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	27
550e3dc0 WH	28	#ifndef __ASSEMBLY__
	29	unsigned long get_board_sys_clk(void);
	30	unsigned long get_board_ddr_clk(void);
	31	#endif
	32
70097027	33	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
d612f0ab AW	34	#define CONFIG_SYS_CLK_FREQ 100000000
	35	#define CONFIG_DDR_CLK_FREQ 100000000
	36	#define CONFIG_QIXIS_I2C_ACCESS
	37	#else
550e3dc0 WH	38	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
550e3dc0 WH	39	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
d612f0ab	40	#endif
550e3dc0	41
86949c2b AW	42	#ifdef CONFIG_RAMBOOT_PBL
	43	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
	44	#endif
	45
	46	#ifdef CONFIG_SD_BOOT
70097027 AW	47	#ifdef CONFIG_SD_BOOT_QSPI
	48	#define CONFIG_SYS_FSL_PBL_RCW \
	49	board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
	50	#else
	51	#define CONFIG_SYS_FSL_PBL_RCW \
	52	board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
	53	#endif
86949c2b	54
86949c2b AW	55	#define CONFIG_SPL_MAX_SIZE 0x1a000
	56	#define CONFIG_SPL_STACK 0x1001d000
	57	#define CONFIG_SPL_PAD_TO 0x1c000
86949c2b	58
41ba57d0	59	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
41ba57d0	60	CONFIG_SYS_MONITOR_LEN)
86949c2b AW	61	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	62	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	63	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
7ee52af4	64	#define CONFIG_SYS_MONITOR_LEN 0xc0000
86949c2b AW	65	#endif
86949c2b AW	66
8ab967b6 AW	67	#ifdef CONFIG_NAND_BOOT
8ab967b6 AW	68	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
8ab967b6	69
8ab967b6 AW	70	#define CONFIG_SPL_MAX_SIZE 0x1a000
	71	#define CONFIG_SPL_STACK 0x1001d000
	72	#define CONFIG_SPL_PAD_TO 0x1c000
8ab967b6 AW	73
	74	#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
	75	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
	76	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	77	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	78	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	79
	80	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	81	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	82	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	83	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	84	#define CONFIG_SYS_MONITOR_LEN 0x80000
	85	#endif
	86
550e3dc0 WH	87	#define CONFIG_DDR_SPD
	88	#define SPD_EEPROM_ADDRESS 0x51
	89	#define CONFIG_SYS_SPD_BUS_NUM 0
550e3dc0	90
c7eae7fc	91	#ifndef CONFIG_SYS_FSL_DDR4
c7eae7fc YS	92	#define CONFIG_SYS_DDR_RAW_TIMING
c7eae7fc YS	93	#endif
550e3dc0 WH	94	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	95	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	96
	97	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	98	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	99
	100	#define CONFIG_DDR_ECC
	101	#ifdef CONFIG_DDR_ECC
	102	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	103	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	104	#endif
	105
550e3dc0 WH	106	/*
	107	* IFC Definitions
	108	*/
70097027	109	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
550e3dc0 WH	110	#define CONFIG_FSL_IFC
	111	#define CONFIG_SYS_FLASH_BASE 0x60000000
	112	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	113
	114	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	115	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	116	CSPR_PORT_SIZE_16 \| \
	117	CSPR_MSEL_NOR \| \
	118	CSPR_V)
	119	#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
	120	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	121	+ 0x8000000) \| \
	122	CSPR_PORT_SIZE_16 \| \
	123	CSPR_MSEL_NOR \| \
	124	CSPR_V)
	125	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	126
	127	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	128	CSOR_NOR_TRHZ_80)
	129	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	130	FTIM0_NOR_TEADC(0x5) \| \
	131	FTIM0_NOR_TEAHC(0x5))
	132	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	133	FTIM1_NOR_TRAD_NOR(0x1a) \| \
	134	FTIM1_NOR_TSEQRAD_NOR(0x13))
	135	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	136	FTIM2_NOR_TCH(0x4) \| \
	137	FTIM2_NOR_TWPH(0xe) \| \
	138	FTIM2_NOR_TWP(0x1c))
	139	#define CONFIG_SYS_NOR_FTIM3 0
	140
550e3dc0 WH	141	#define CONFIG_SYS_FLASH_QUIET_TEST
	142	#define CONFIG_FLASH_SHOW_PROGRESS 45
	143	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	144	#define CONFIG_SYS_WRITE_SWAPPED_DATA
550e3dc0 WH	145
	146	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	147	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	148	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	149	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	150
	151	#define CONFIG_SYS_FLASH_EMPTY_INFO
	152	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
	153	CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
	154
	155	/*
	156	* NAND Flash Definitions
	157	*/
	158	#define CONFIG_NAND_FSL_IFC
	159
	160	#define CONFIG_SYS_NAND_BASE 0x7e800000
	161	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	162
	163	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	164
	165	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	166	\| CSPR_PORT_SIZE_8 \
	167	\| CSPR_MSEL_NAND \
	168	\| CSPR_V)
	169	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	170	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	171	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	172	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	173	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	174	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	175	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	176	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	177
	178	#define CONFIG_SYS_NAND_ONFI_DETECTION
	179
	180	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	181	FTIM0_NAND_TWP(0x18) \| \
	182	FTIM0_NAND_TWCHT(0x7) \| \
	183	FTIM0_NAND_TWH(0xa))
	184	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	185	FTIM1_NAND_TWBE(0x39) \| \
	186	FTIM1_NAND_TRR(0xe) \| \
	187	FTIM1_NAND_TRP(0x18))
	188	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	189	FTIM2_NAND_TREH(0xa) \| \
	190	FTIM2_NAND_TWHRE(0x1e))
	191	#define CONFIG_SYS_NAND_FTIM3 0x0
	192
	193	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	194	#define CONFIG_SYS_MAX_NAND_DEVICE 1
550e3dc0 WH	195
550e3dc0 WH	196	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
d612f0ab	197	#endif
550e3dc0 WH	198
	199	/*
	200	* QIXIS Definitions
	201	*/
	202	#define CONFIG_FSL_QIXIS
	203
	204	#ifdef CONFIG_FSL_QIXIS
	205	#define QIXIS_BASE 0x7fb00000
	206	#define QIXIS_BASE_PHYS QIXIS_BASE
	207	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	208	#define QIXIS_LBMAP_SWITCH 6
	209	#define QIXIS_LBMAP_MASK 0x0f
	210	#define QIXIS_LBMAP_SHIFT 0
	211	#define QIXIS_LBMAP_DFLTBANK 0x00
	212	#define QIXIS_LBMAP_ALTBANK 0x04
aeb901f2 HZ	213	#define QIXIS_PWR_CTL 0x21
aeb901f2 HZ	214	#define QIXIS_PWR_CTL_POWEROFF 0x80
550e3dc0 WH	215	#define QIXIS_RST_CTL_RESET 0x44
	216	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	217	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	218	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
349cfc97 HZ	219	#define QIXIS_CTL_SYS 0x5
	220	#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
	221	#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
	222	#define QIXIS_RST_FORCE_3 0x45
	223	#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
	224	#define QIXIS_PWR_CTL2 0x21
	225	#define QIXIS_PWR_CTL2_PCTL 0x2
550e3dc0 WH	226
	227	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	228	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
	229	CSPR_PORT_SIZE_8 \| \
	230	CSPR_MSEL_GPCM \| \
	231	CSPR_V)
	232	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	233	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	234	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	235	CSOR_NOR_TRHZ_80)
	236
	237	/*
	238	* QIXIS Timing parameters for IFC GPCM
	239	*/
	240	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) \| \
	241	FTIM0_GPCM_TEADC(0xe) \| \
	242	FTIM0_GPCM_TEAHC(0xe))
	243	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) \| \
	244	FTIM1_GPCM_TRAD(0x1f))
	245	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) \| \
	246	FTIM2_GPCM_TCH(0xe) \| \
	247	FTIM2_GPCM_TWP(0xf0))
	248	#define CONFIG_SYS_FPGA_FTIM3 0x0
	249	#endif
	250
8ab967b6 AW	251	#if defined(CONFIG_NAND_BOOT)
	252	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	253	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	254	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	255	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	256	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	257	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	258	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	259	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	260	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	261	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	262	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	263	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	264	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	265	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	266	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	267	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	268	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
	269	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
	270	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	271	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	272	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	273	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	274	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	275	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	276	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	277	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	278	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	279	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	280	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	281	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	282	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	283	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
	284	#else
550e3dc0 WH	285	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	286	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	287	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	288	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	289	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	290	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	291	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	292	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	293	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
	294	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
	295	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	296	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	297	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	298	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	299	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	300	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	301	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	302	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	303	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	304	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	305	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	306	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	307	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	308	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	309	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	310	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	311	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	312	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	313	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	314	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	315	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	316	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
8ab967b6	317	#endif
550e3dc0 WH	318
	319	/*
	320	* Serial Port
	321	*/
8fc2121a	322	#ifdef CONFIG_LPUART
8fc2121a AW	323	#define CONFIG_LPUART_32B_REG
8fc2121a AW	324	#else
550e3dc0	325	#define CONFIG_SYS_NS16550_SERIAL
d83b47b7	326	#ifndef CONFIG_DM_SERIAL
550e3dc0	327	#define CONFIG_SYS_NS16550_REG_SIZE 1
d83b47b7	328	#endif
550e3dc0	329	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
8fc2121a	330	#endif
550e3dc0	331
550e3dc0 WH	332	/*
	333	* I2C
	334	*/
9ebde884	335	#ifndef CONFIG_DM_I2C
550e3dc0	336	#define CONFIG_SYS_I2C
9ebde884 BL	337	#else
	338	#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
	339	#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
	340	#endif
550e3dc0	341	#define CONFIG_SYS_I2C_MXC
03544c66 AA	342	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	343	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	344	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
550e3dc0	345
73dc91f9 JG	346	/* EEPROM */
	347	#define CONFIG_ID_EEPROM
	348	#define CONFIG_SYS_I2C_EEPROM_NXID
	349	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	350	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	351	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	352	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	353	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	354
550e3dc0 WH	355	/*
	356	* I2C bus multiplexer
	357	*/
	358	#define I2C_MUX_PCA_ADDR_PRI 0x77
	359	#define I2C_MUX_CH_DEFAULT 0x8
dd04832d	360	#define I2C_MUX_CH_CH7301 0xC
550e3dc0 WH	361
	362	/*
	363	* MMC
	364	*/
550e3dc0	365
e5493d4e	366	/* SPI */
70097027	367	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
e5493d4e	368	/* QSPI */
d612f0ab AW	369	#define QSPI0_AMBA_BASE 0x40000000
	370	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	371	#define FSL_QSPI_FLASH_NUM 2
	372
e5493d4e	373	/* DSPI */
e5493d4e HW	374
	375	/* DM SPI */
	376	#if defined(CONFIG_FSL_DSPI) \|\| defined(CONFIG_FSL_QSPI)
e5493d4e	377	#define CONFIG_DM_SPI_FLASH
6812484a	378	#define CONFIG_SPI_FLASH_DATAFLASH
e5493d4e	379	#endif
d612f0ab AW	380	#endif
d612f0ab AW	381
dd04832d XL	382	/*
	383	* Video
	384	*/
b215fb3f	385	#ifdef CONFIG_VIDEO_FSL_DCU_FB
dd04832d XL	386	#define CONFIG_VIDEO_LOGO
	387	#define CONFIG_VIDEO_BMP_LOGO
	388
	389	#define CONFIG_FSL_DIU_CH7301
	390	#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
	391	#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
	392	#define CONFIG_SYS_I2C_DVI_ADDR 0x75
	393	#endif
	394
550e3dc0 WH	395	/*
	396	* eTSEC
	397	*/
550e3dc0 WH	398
550e3dc0 WH	399	#ifdef CONFIG_TSEC_ENET
550e3dc0 WH	400	#define CONFIG_MII_DEFAULT_TSEC 3
	401	#define CONFIG_TSEC1 1
	402	#define CONFIG_TSEC1_NAME "eTSEC1"
	403	#define CONFIG_TSEC2 1
	404	#define CONFIG_TSEC2_NAME "eTSEC2"
	405	#define CONFIG_TSEC3 1
	406	#define CONFIG_TSEC3_NAME "eTSEC3"
	407
	408	#define TSEC1_PHY_ADDR 1
	409	#define TSEC2_PHY_ADDR 2
	410	#define TSEC3_PHY_ADDR 3
	411
	412	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	413	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	414	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	415
	416	#define TSEC1_PHYIDX 0
	417	#define TSEC2_PHYIDX 0
	418	#define TSEC3_PHYIDX 0
	419
	420	#define CONFIG_ETHPRIME "eTSEC1"
	421
550e3dc0 WH	422	#define CONFIG_HAS_ETH0
	423	#define CONFIG_HAS_ETH1
	424	#define CONFIG_HAS_ETH2
	425
	426	#define CONFIG_FSL_SGMII_RISER 1
	427	#define SGMII_RISER_PHY_OFFSET 0x1b
	428
	429	#ifdef CONFIG_FSL_SGMII_RISER
	430	#define CONFIG_SYS_TBIPA_VALUE 8
	431	#endif
	432
	433	#endif
da419027 ML	434
da419027 ML	435	/* PCIe */
b38eaec5 RD	436	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	437	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	438
180b8688	439	#ifdef CONFIG_PCI
180b8688	440	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	441	#endif
180b8688 ML	442
550e3dc0	443	#define CONFIG_CMDLINE_TAG
86949c2b	444
1a2826f6	445	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	446	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	447	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	448	#define COUNTER_FREQUENCY 12500000
1a2826f6	449
550e3dc0	450	#define CONFIG_HWCONFIG
03c22449 ZZ	451	#define HWCONFIG_BUFFER_SIZE 256
	452
	453	#define CONFIG_FSL_DEVICE_DISABLE
550e3dc0	454
550e3dc0	455
615bfce5	456	#define CONFIG_SYS_QE_FW_ADDR 0x60940000
63e75fd7	457
8fc2121a AW	458	#ifdef CONFIG_LPUART
	459	#define CONFIG_EXTRA_ENV_SETTINGS \
	460	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
99fe4541	461	"initrd_high=0xffffffff\0" \
8fc2121a AW	462	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
8fc2121a AW	463	#else
550e3dc0 WH	464	#define CONFIG_EXTRA_ENV_SETTINGS \
550e3dc0 WH	465	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
99fe4541	466	"initrd_high=0xffffffff\0" \
550e3dc0	467	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
8fc2121a	468	#endif
550e3dc0 WH	469
	470	/*
	471	* Miscellaneous configurable options
	472	*/
c463eeb4	473	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
550e3dc0	474
550e3dc0	475	#define CONFIG_SYS_LOAD_ADDR 0x82000000
550e3dc0	476
660673af XL	477	#define CONFIG_LS102XA_STREAM_ID
660673af XL	478
550e3dc0 WH	479	#define CONFIG_SYS_INIT_SP_OFFSET \
	480	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	481	#define CONFIG_SYS_INIT_SP_ADDR \
	482	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	483
86949c2b AW	484	#ifdef CONFIG_SPL_BUILD
	485	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	486	#else
550e3dc0	487	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
86949c2b	488	#endif
550e3dc0 WH	489
	490	/*
	491	* Environment
	492	*/
	493	#define CONFIG_ENV_OVERWRITE
	494
86949c2b	495	#if defined(CONFIG_SD_BOOT)
86949c2b	496	#define CONFIG_SYS_MMC_ENV_DEV 0
86949c2b	497	#endif
550e3dc0	498
ef6c55a2	499	#include <asm/fsl_secure_boot.h>
cc7b8b9a	500	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	501
550e3dc0	502	#endif