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550e3dc0 WH |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | #include <config_cmd_default.h> | |
11 | ||
12 | #define CONFIG_LS102XA | |
13 | ||
14 | #define CONFIG_SYS_GENERIC_BOARD | |
15 | ||
16 | #define CONFIG_DISPLAY_CPUINFO | |
17 | #define CONFIG_DISPLAY_BOARDINFO | |
18 | ||
19 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
20 | #define CONFIG_BOARD_EARLY_INIT_F | |
21 | ||
22 | /* | |
23 | * Size of malloc() pool | |
24 | */ | |
25 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
26 | ||
27 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
28 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
29 | ||
30 | /* | |
31 | * Generic Timer Definitions | |
32 | */ | |
33 | #define GENERIC_TIMER_CLK 12500000 | |
34 | ||
35 | #ifndef __ASSEMBLY__ | |
36 | unsigned long get_board_sys_clk(void); | |
37 | unsigned long get_board_ddr_clk(void); | |
38 | #endif | |
39 | ||
40 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
41 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
42 | ||
43 | #ifndef CONFIG_SYS_TEXT_BASE | |
44 | #define CONFIG_SYS_TEXT_BASE 0x67f80000 | |
45 | #endif | |
46 | ||
47 | #define CONFIG_NR_DRAM_BANKS 1 | |
48 | ||
49 | #define CONFIG_DDR_SPD | |
50 | #define SPD_EEPROM_ADDRESS 0x51 | |
51 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
550e3dc0 WH |
52 | |
53 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ | |
c7eae7fc | 54 | #ifndef CONFIG_SYS_FSL_DDR4 |
550e3dc0 | 55 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ |
c7eae7fc YS |
56 | #define CONFIG_SYS_DDR_RAW_TIMING |
57 | #endif | |
550e3dc0 WH |
58 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
59 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
60 | ||
61 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
62 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
63 | ||
64 | #define CONFIG_DDR_ECC | |
65 | #ifdef CONFIG_DDR_ECC | |
66 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
67 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
68 | #endif | |
69 | ||
70 | #define CONFIG_SYS_HAS_SERDES | |
71 | ||
72 | /* | |
73 | * IFC Definitions | |
74 | */ | |
75 | #define CONFIG_FSL_IFC | |
76 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
77 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
78 | ||
79 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
80 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
81 | CSPR_PORT_SIZE_16 | \ | |
82 | CSPR_MSEL_NOR | \ | |
83 | CSPR_V) | |
84 | #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) | |
85 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
86 | + 0x8000000) | \ | |
87 | CSPR_PORT_SIZE_16 | \ | |
88 | CSPR_MSEL_NOR | \ | |
89 | CSPR_V) | |
90 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
91 | ||
92 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
93 | CSOR_NOR_TRHZ_80) | |
94 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
95 | FTIM0_NOR_TEADC(0x5) | \ | |
96 | FTIM0_NOR_TEAHC(0x5)) | |
97 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
98 | FTIM1_NOR_TRAD_NOR(0x1a) | \ | |
99 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
100 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
101 | FTIM2_NOR_TCH(0x4) | \ | |
102 | FTIM2_NOR_TWPH(0xe) | \ | |
103 | FTIM2_NOR_TWP(0x1c)) | |
104 | #define CONFIG_SYS_NOR_FTIM3 0 | |
105 | ||
106 | #define CONFIG_FLASH_CFI_DRIVER | |
107 | #define CONFIG_SYS_FLASH_CFI | |
108 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
109 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
110 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
111 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
112 | ||
113 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
114 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
115 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
116 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
117 | ||
118 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
119 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ | |
120 | CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} | |
121 | ||
122 | /* | |
123 | * NAND Flash Definitions | |
124 | */ | |
125 | #define CONFIG_NAND_FSL_IFC | |
126 | ||
127 | #define CONFIG_SYS_NAND_BASE 0x7e800000 | |
128 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
129 | ||
130 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
131 | ||
132 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
133 | | CSPR_PORT_SIZE_8 \ | |
134 | | CSPR_MSEL_NAND \ | |
135 | | CSPR_V) | |
136 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
137 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
138 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
139 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
140 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ | |
141 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
142 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | |
143 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ | |
144 | ||
145 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
146 | ||
147 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ | |
148 | FTIM0_NAND_TWP(0x18) | \ | |
149 | FTIM0_NAND_TWCHT(0x7) | \ | |
150 | FTIM0_NAND_TWH(0xa)) | |
151 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
152 | FTIM1_NAND_TWBE(0x39) | \ | |
153 | FTIM1_NAND_TRR(0xe) | \ | |
154 | FTIM1_NAND_TRP(0x18)) | |
155 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ | |
156 | FTIM2_NAND_TREH(0xa) | \ | |
157 | FTIM2_NAND_TWHRE(0x1e)) | |
158 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
159 | ||
160 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
161 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
162 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
163 | #define CONFIG_CMD_NAND | |
164 | ||
165 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
166 | ||
167 | /* | |
168 | * QIXIS Definitions | |
169 | */ | |
170 | #define CONFIG_FSL_QIXIS | |
171 | ||
172 | #ifdef CONFIG_FSL_QIXIS | |
173 | #define QIXIS_BASE 0x7fb00000 | |
174 | #define QIXIS_BASE_PHYS QIXIS_BASE | |
175 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
176 | #define QIXIS_LBMAP_SWITCH 6 | |
177 | #define QIXIS_LBMAP_MASK 0x0f | |
178 | #define QIXIS_LBMAP_SHIFT 0 | |
179 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
180 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
181 | #define QIXIS_RST_CTL_RESET 0x44 | |
182 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
183 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
184 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
185 | ||
186 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
187 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ | |
188 | CSPR_PORT_SIZE_8 | \ | |
189 | CSPR_MSEL_GPCM | \ | |
190 | CSPR_V) | |
191 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
192 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
193 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
194 | CSOR_NOR_TRHZ_80) | |
195 | ||
196 | /* | |
197 | * QIXIS Timing parameters for IFC GPCM | |
198 | */ | |
199 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ | |
200 | FTIM0_GPCM_TEADC(0xe) | \ | |
201 | FTIM0_GPCM_TEAHC(0xe)) | |
202 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ | |
203 | FTIM1_GPCM_TRAD(0x1f)) | |
204 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ | |
205 | FTIM2_GPCM_TCH(0xe) | \ | |
206 | FTIM2_GPCM_TWP(0xf0)) | |
207 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
208 | #endif | |
209 | ||
210 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
211 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
212 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
213 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
214 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
215 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
216 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
217 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
218 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
219 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
220 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
221 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
222 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
223 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
224 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
225 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
226 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
227 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
228 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
229 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
230 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
231 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
232 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
233 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
234 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
235 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
236 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
237 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
238 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
239 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
240 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
241 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
242 | ||
243 | /* | |
244 | * Serial Port | |
245 | */ | |
246 | #define CONFIG_CONS_INDEX 1 | |
247 | #define CONFIG_SYS_NS16550 | |
248 | #define CONFIG_SYS_NS16550_SERIAL | |
249 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
250 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
251 | ||
252 | #define CONFIG_BAUDRATE 115200 | |
253 | ||
254 | /* | |
255 | * I2C | |
256 | */ | |
257 | #define CONFIG_CMD_I2C | |
258 | #define CONFIG_SYS_I2C | |
259 | #define CONFIG_SYS_I2C_MXC | |
260 | ||
261 | /* | |
262 | * I2C bus multiplexer | |
263 | */ | |
264 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
265 | #define I2C_MUX_CH_DEFAULT 0x8 | |
266 | ||
267 | /* | |
268 | * MMC | |
269 | */ | |
270 | #define CONFIG_MMC | |
271 | #define CONFIG_CMD_MMC | |
272 | #define CONFIG_FSL_ESDHC | |
273 | #define CONFIG_GENERIC_MMC | |
274 | ||
275 | /* | |
276 | * eTSEC | |
277 | */ | |
278 | #define CONFIG_TSEC_ENET | |
279 | ||
280 | #ifdef CONFIG_TSEC_ENET | |
281 | #define CONFIG_MII | |
282 | #define CONFIG_MII_DEFAULT_TSEC 3 | |
283 | #define CONFIG_TSEC1 1 | |
284 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
285 | #define CONFIG_TSEC2 1 | |
286 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
287 | #define CONFIG_TSEC3 1 | |
288 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
289 | ||
290 | #define TSEC1_PHY_ADDR 1 | |
291 | #define TSEC2_PHY_ADDR 2 | |
292 | #define TSEC3_PHY_ADDR 3 | |
293 | ||
294 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
295 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
296 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
297 | ||
298 | #define TSEC1_PHYIDX 0 | |
299 | #define TSEC2_PHYIDX 0 | |
300 | #define TSEC3_PHYIDX 0 | |
301 | ||
302 | #define CONFIG_ETHPRIME "eTSEC1" | |
303 | ||
304 | #define CONFIG_PHY_GIGE | |
305 | #define CONFIG_PHYLIB | |
306 | #define CONFIG_PHY_REALTEK | |
307 | ||
308 | #define CONFIG_HAS_ETH0 | |
309 | #define CONFIG_HAS_ETH1 | |
310 | #define CONFIG_HAS_ETH2 | |
311 | ||
312 | #define CONFIG_FSL_SGMII_RISER 1 | |
313 | #define SGMII_RISER_PHY_OFFSET 0x1b | |
314 | ||
315 | #ifdef CONFIG_FSL_SGMII_RISER | |
316 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
317 | #endif | |
318 | ||
319 | #endif | |
320 | #define CONFIG_CMD_PING | |
321 | #define CONFIG_CMD_DHCP | |
322 | #define CONFIG_CMD_MII | |
323 | #define CONFIG_CMD_NET | |
324 | ||
325 | #define CONFIG_CMDLINE_TAG | |
326 | #define CONFIG_CMDLINE_EDITING | |
327 | #define CONFIG_CMD_IMLS | |
328 | ||
329 | #define CONFIG_HWCONFIG | |
330 | #define HWCONFIG_BUFFER_SIZE 128 | |
331 | ||
332 | #define CONFIG_BOOTDELAY 3 | |
333 | ||
334 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
335 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
336 | "fdt_high=0xcfffffff\0" \ | |
337 | "initrd_high=0xcfffffff\0" \ | |
338 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" | |
339 | ||
340 | /* | |
341 | * Miscellaneous configurable options | |
342 | */ | |
343 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
344 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
345 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
346 | #define CONFIG_SYS_PROMPT "=> " | |
347 | #define CONFIG_AUTO_COMPLETE | |
348 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
349 | #define CONFIG_SYS_PBSIZE \ | |
350 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
351 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
352 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
353 | ||
354 | #define CONFIG_CMD_ENV_EXISTS | |
355 | #define CONFIG_CMD_GREPENV | |
356 | #define CONFIG_CMD_MEMINFO | |
357 | #define CONFIG_CMD_MEMTEST | |
358 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
359 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
360 | ||
361 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
362 | #define CONFIG_SYS_HZ 1000 | |
363 | ||
364 | /* | |
365 | * Stack sizes | |
366 | * The stack sizes are set up in start.S using the settings below | |
367 | */ | |
368 | #define CONFIG_STACKSIZE (30 * 1024) | |
369 | ||
370 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
371 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
372 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
373 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
374 | ||
375 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
376 | ||
377 | /* | |
378 | * Environment | |
379 | */ | |
380 | #define CONFIG_ENV_OVERWRITE | |
381 | ||
382 | #define CONFIG_ENV_IS_IN_FLASH | |
383 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
384 | #define CONFIG_ENV_SIZE 0x2000 | |
385 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
386 | ||
387 | #define CONFIG_OF_LIBFDT | |
388 | #define CONFIG_OF_BOARD_SETUP | |
389 | #define CONFIG_CMD_BOOTZ | |
390 | ||
391 | #endif |