[thirdparty/u-boot.git] / include / configs / ls1021atwr.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2019 NXP
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_DEEP_SLEEP

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define DDR_SDRAM_CFG			0x470c0008
#define DDR_CS0_BNDS			0x008000bf
#define DDR_CS0_CONFIG			0x80014302
#define DDR_TIMING_CFG_0		0x50550004
#define DDR_TIMING_CFG_1		0xbcb38c56
#define DDR_TIMING_CFG_2		0x0040d120
#define DDR_TIMING_CFG_3		0x010e1000
#define DDR_TIMING_CFG_4		0x00000001
#define DDR_TIMING_CFG_5		0x03401400
#define DDR_SDRAM_CFG_2			0x00401010
#define DDR_SDRAM_MODE			0x00061c60
#define DDR_SDRAM_MODE_2		0x00180000
#define DDR_SDRAM_INTERVAL		0x18600618
#define DDR_DDR_WRLVL_CNTL		0x8655f605
#define DDR_DDR_WRLVL_CNTL_2		0x05060607
#define DDR_DDR_WRLVL_CNTL_3		0x05050505
#define DDR_DDR_CDR1			0x80040000
#define DDR_DDR_CDR2			0x00000001
#define DDR_SDRAM_CLK_CNTL		0x02000000
#define DDR_DDR_ZQ_CNTL			0x89080600
#define DDR_CS0_CONFIG_2		0
#define DDR_SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG_BI			0x00000001

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW	\
	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif

#ifdef CONFIG_NXP_ESBC
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image.
 */
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_NXP_ESBC */

#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif

#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_CHIP_SELECTS_PER_CTRL	4

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1A) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWP(0x1c) | \
					FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif

/* CPLD */

#define CONFIG_SYS_CPLD_BASE	0x7fb00000
#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		1
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * MMC
 */

/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

/* DSPI */
#endif

/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_DM_SPI_FLASH
#endif

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
#define CONFIG_SYS_I2C_DVI_ADDR		0x39
#endif

/*
 * eTSEC
 */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME			"ethernet@2d10000"
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

#define CONFIG_CMDLINE_TAG

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE

#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "	\
		"cma=64M@0x0-0xb0000000\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x65000000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	"kernel_addr_sd=0x8000\0"	\
	"kernel_size_sd=0x14000\0"	\
	"othbootargs=cma=64M@0x0-0xb0000000\0"	\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
			"env exists secureboot "	\
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"installer=load mmc 0:2 $load_addr "	\
		"/flex_installer_arm32.itb; "		\
		"bootm $load_addr#ls1021atwr\0"	\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size && bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size && bootm $load_addr#$board\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200 "	\
		"cma=64M@0x0-0xb0000000\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x61000000\0"	\
	"kernelheader_addr=0x60800000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"kernelheader_size=0x40000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	"kernel_addr_sd=0x8000\0"	\
	"kernel_size_sd=0x14000\0"	\
	"kernelhdr_addr_sd=0x4000\0"		\
	"kernelhdr_size_sd=0x10\0"		\
	"othbootargs=cma=64M@0x0-0xb0000000\0"	\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0" \
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size; env exists secureboot "	\
		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"sd_bootcmd=echo Trying load from SD ..;"       \
		"mmcinfo && mmc read $load_addr "	\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r "		\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"
#endif

#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
			   "env exists secureboot && esbc_halt"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#else
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"	\
			   "env exists secureboot && esbc_halt;"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#undef CONFIG_DM_I2C
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

#define CONFIG_SYS_QE_FW_ADDR     0x60940000

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV		0
#endif

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c8a7d9da WH	2	/*
c8a7d9da WH	3	* Copyright 2014 Freescale Semiconductor, Inc.
9ebde884	4	* Copyright 2019 NXP
c8a7d9da WH	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
aeb901f2	10	#define CONFIG_ARMV7_PSCI_1_0
340848b1	11
3288628a HZ	12	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	13
18fb0e3c	14	#define CONFIG_SYS_FSL_CLK
c8a7d9da	15
c8a7d9da	16	#define CONFIG_SKIP_LOWLEVEL_INIT
99e1bd42	17	#define CONFIG_DEEP_SLEEP
c8a7d9da WH	18
	19	/*
	20	* Size of malloc() pool
	21	*/
	22	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	23
	24	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	25	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	26
c8a7d9da WH	27	#define CONFIG_SYS_CLK_FREQ 100000000
	28	#define CONFIG_DDR_CLK_FREQ 100000000
	29
a88cc3bd YS	30	#define DDR_SDRAM_CFG 0x470c0008
	31	#define DDR_CS0_BNDS 0x008000bf
	32	#define DDR_CS0_CONFIG 0x80014302
	33	#define DDR_TIMING_CFG_0 0x50550004
	34	#define DDR_TIMING_CFG_1 0xbcb38c56
	35	#define DDR_TIMING_CFG_2 0x0040d120
	36	#define DDR_TIMING_CFG_3 0x010e1000
	37	#define DDR_TIMING_CFG_4 0x00000001
	38	#define DDR_TIMING_CFG_5 0x03401400
	39	#define DDR_SDRAM_CFG_2 0x00401010
	40	#define DDR_SDRAM_MODE 0x00061c60
	41	#define DDR_SDRAM_MODE_2 0x00180000
	42	#define DDR_SDRAM_INTERVAL 0x18600618
	43	#define DDR_DDR_WRLVL_CNTL 0x8655f605
	44	#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	45	#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	46	#define DDR_DDR_CDR1 0x80040000
	47	#define DDR_DDR_CDR2 0x00000001
	48	#define DDR_SDRAM_CLK_CNTL 0x02000000
	49	#define DDR_DDR_ZQ_CNTL 0x89080600
	50	#define DDR_CS0_CONFIG_2 0
	51	#define DDR_SDRAM_CFG_MEM_EN 0x80000000
99e1bd42 TY	52	#define SDRAM_CFG2_D_INIT 0x00000010
	53	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
	54	#define SDRAM_CFG2_FRC_SR 0x80000000
	55	#define SDRAM_CFG_BI 0x00000001
a88cc3bd	56
8415bb68 AW	57	#ifdef CONFIG_RAMBOOT_PBL
	58	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
	59	#endif
	60
	61	#ifdef CONFIG_SD_BOOT
947cee11 AW	62	#ifdef CONFIG_SD_BOOT_QSPI
	63	#define CONFIG_SYS_FSL_PBL_RCW \
	64	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
	65	#else
	66	#define CONFIG_SYS_FSL_PBL_RCW \
	67	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
	68	#endif
e7e720c2	69
5536c3c9	70	#ifdef CONFIG_NXP_ESBC
e7e720c2 SG	71	/*
	72	* HDR would be appended at end of image and copied to DDR along
	73	* with U-Boot image.
	74	*/
693d4c9f	75	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
5536c3c9	76	#endif /* ifdef CONFIG_NXP_ESBC */
8415bb68	77
8415bb68 AW	78	#define CONFIG_SPL_MAX_SIZE 0x1a000
	79	#define CONFIG_SPL_STACK 0x1001d000
	80	#define CONFIG_SPL_PAD_TO 0x1c000
8415bb68	81
99e1bd42 TY	82	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
99e1bd42 TY	83	CONFIG_SYS_MONITOR_LEN)
8415bb68 AW	84	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	85	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	86	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
e7e720c2 SG	87
	88	#ifdef CONFIG_U_BOOT_HDR_SIZE
	89	/*
	90	* HDR would be appended at end of image and copied to DDR along
	91	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	92	* size increases then increase this size in case of secure boot as
	93	* it uses raw u-boot image instead of fit image.
	94	*/
9b6639fa	95	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
e7e720c2	96	#else
9b6639fa	97	#define CONFIG_SYS_MONITOR_LEN 0x100000
e7e720c2	98	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
8415bb68 AW	99	#endif
8415bb68 AW	100
c8a7d9da WH	101	#define PHYS_SDRAM 0x80000000
	102	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	103
	104	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	105	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	106
15809705 AW	107	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
15809705 AW	108
c8a7d9da WH	109	/*
	110	* IFC Definitions
	111	*/
947cee11	112	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
c8a7d9da WH	113	#define CONFIG_FSL_IFC
	114	#define CONFIG_SYS_FLASH_BASE 0x60000000
	115	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	116
	117	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	118	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	119	CSPR_PORT_SIZE_16 \| \
	120	CSPR_MSEL_NOR \| \
	121	CSPR_V)
	122	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	123
	124	/* NOR Flash Timing Params */
	125	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	126	CSOR_NOR_TRHZ_80)
	127	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	128	FTIM0_NOR_TEADC(0x5) \| \
	129	FTIM0_NOR_TAVDS(0x0) \| \
	130	FTIM0_NOR_TEAHC(0x5))
	131	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	132	FTIM1_NOR_TRAD_NOR(0x1A) \| \
	133	FTIM1_NOR_TSEQRAD_NOR(0x13))
	134	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	135	FTIM2_NOR_TCH(0x4) \| \
	136	FTIM2_NOR_TWP(0x1c) \| \
	137	FTIM2_NOR_TWPH(0x0e))
	138	#define CONFIG_SYS_NOR_FTIM3 0
	139
c8a7d9da WH	140	#define CONFIG_SYS_FLASH_QUIET_TEST
	141	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	142
	143	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	144	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	145	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	146	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	147
	148	#define CONFIG_SYS_FLASH_EMPTY_INFO
	149	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	150
	151	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	152	#define CONFIG_SYS_WRITE_SWAPPED_DATA
d612f0ab	153	#endif
c8a7d9da WH	154
	155	/* CPLD */
	156
	157	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	158	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	159
	160	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	161	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	162	CSPR_PORT_SIZE_8 \| \
	163	CSPR_MSEL_GPCM \| \
	164	CSPR_V)
	165	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	166	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	167	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	168	CSOR_NOR_TRHZ_80)
	169
	170	/* CPLD Timing parameters for IFC GPCM */
	171	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	172	FTIM0_GPCM_TEADC(0xf) \| \
	173	FTIM0_GPCM_TEAHC(0xf))
	174	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	175	FTIM1_GPCM_TRAD(0x3f))
	176	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	177	FTIM2_GPCM_TCH(0xf) \| \
	178	FTIM2_GPCM_TWP(0xff))
	179	#define CONFIG_SYS_FPGA_FTIM3 0x0
	180	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	181	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	182	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	183	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	184	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	185	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	186	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	187	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	188	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
	189	#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
	190	#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
	191	#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
	192	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
	193	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
	194	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
	195	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
	196
	197	/*
	198	* Serial Port
	199	*/
55d53ab4	200	#ifdef CONFIG_LPUART
55d53ab4 AW	201	#define CONFIG_LPUART_32B_REG
55d53ab4 AW	202	#else
c8a7d9da	203	#define CONFIG_SYS_NS16550_SERIAL
f833cd62	204	#ifndef CONFIG_DM_SERIAL
c8a7d9da	205	#define CONFIG_SYS_NS16550_REG_SIZE 1
f833cd62	206	#endif
c8a7d9da	207	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
55d53ab4	208	#endif
c8a7d9da	209
c8a7d9da WH	210	/*
	211	* I2C
	212	*/
9ebde884	213	#ifndef CONFIG_DM_I2C
c8a7d9da	214	#define CONFIG_SYS_I2C
9ebde884 BL	215	#else
	216	#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
	217	#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
	218	#endif
c8a7d9da	219	#define CONFIG_SYS_I2C_MXC
03544c66 AA	220	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	221	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	222	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
c8a7d9da	223
5175a288	224	/* EEPROM */
5175a288 AW	225	#define CONFIG_ID_EEPROM
	226	#define CONFIG_SYS_I2C_EEPROM_NXID
	227	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	228	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	229	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	230	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	231	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
5175a288	232
c8a7d9da WH	233	/*
	234	* MMC
	235	*/
c8a7d9da	236
9dd3d3c0	237	/* SPI */
947cee11	238	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9dd3d3c0	239	/* QSPI */
d612f0ab AW	240	#define QSPI0_AMBA_BASE 0x40000000
	241	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	242	#define FSL_QSPI_FLASH_NUM 2
	243
03d1d568	244	/* DSPI */
03d1d568 YY	245	#endif
03d1d568 YY	246
9dd3d3c0 HW	247	/* DM SPI */
9dd3d3c0 HW	248	#if defined(CONFIG_FSL_DSPI) \|\| defined(CONFIG_FSL_QSPI)
9dd3d3c0 HW	249	#define CONFIG_DM_SPI_FLASH
9dd3d3c0 HW	250	#endif
d612f0ab	251
b4ecc8c6 WH	252	/*
	253	* Video
	254	*/
b215fb3f	255	#ifdef CONFIG_VIDEO_FSL_DCU_FB
b4ecc8c6 WH	256	#define CONFIG_VIDEO_LOGO
	257	#define CONFIG_VIDEO_BMP_LOGO
	258
	259	#define CONFIG_FSL_DCU_SII9022A
	260	#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
	261	#define CONFIG_SYS_I2C_DVI_ADDR 0x39
	262	#endif
	263
c8a7d9da WH	264	/*
	265	* eTSEC
	266	*/
c8a7d9da WH	267
c8a7d9da WH	268	#ifdef CONFIG_TSEC_ENET
f588b4d2	269	#define CONFIG_ETHPRIME "ethernet@2d10000"
c8a7d9da WH	270	#endif
c8a7d9da WH	271
da419027	272	/* PCIe */
b38eaec5 RD	273	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	274	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	275
180b8688	276	#ifdef CONFIG_PCI
180b8688	277	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	278	#endif
180b8688 ML	279
c8a7d9da	280	#define CONFIG_CMDLINE_TAG
8415bb68	281
1a2826f6	282	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	283	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	284	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	285	#define COUNTER_FREQUENCY 12500000
1a2826f6	286
c8a7d9da	287	#define CONFIG_HWCONFIG
03c22449 ZZ	288	#define HWCONFIG_BUFFER_SIZE 256
	289
	290	#define CONFIG_FSL_DEVICE_DISABLE
c8a7d9da	291
a65d7408 AW	292	#define BOOT_TARGET_DEVICES(func) \
a65d7408 AW	293	func(MMC, mmc, 0) \
d2c49aad YD	294	func(USB, usb, 0) \
d2c49aad YD	295	func(DHCP, dhcp, na)
a65d7408	296	#include <config_distro_bootcmd.h>
c8a7d9da	297
55d53ab4 AW	298	#ifdef CONFIG_LPUART
55d53ab4 AW	299	#define CONFIG_EXTRA_ENV_SETTINGS \
33c3dfd2 AW	300	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
33c3dfd2 AW	301	"cma=64M@0x0-0xb0000000\0" \
7ff7166c	302	"initrd_high=0xffffffff\0" \
a65d7408 AW	303	"fdt_addr=0x64f00000\0" \
	304	"kernel_addr=0x65000000\0" \
	305	"scriptaddr=0x80000000\0" \
b8ae6798	306	"scripthdraddr=0x80080000\0" \
a65d7408 AW	307	"fdtheader_addr_r=0x80100000\0" \
	308	"kernelheader_addr_r=0x80200000\0" \
	309	"kernel_addr_r=0x81000000\0" \
	310	"fdt_addr_r=0x90000000\0" \
	311	"ramdisk_addr_r=0xa0000000\0" \
	312	"load_addr=0xa0000000\0" \
	313	"kernel_size=0x2800000\0" \
397a173e SL	314	"kernel_addr_sd=0x8000\0" \
397a173e SL	315	"kernel_size_sd=0x14000\0" \
feb8fa2e	316	"othbootargs=cma=64M@0x0-0xb0000000\0" \
a65d7408 AW	317	BOOTENV \
a65d7408 AW	318	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	319	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	320	"scan_dev_for_boot_part=" \
	321	"part list ${devtype} ${devnum} devplist; " \
	322	"env exists devplist \|\| setenv devplist 1; " \
	323	"for distro_bootpart in ${devplist}; do " \
	324	"if fstype ${devtype} " \
	325	"${devnum}:${distro_bootpart} " \
	326	"bootfstype; then " \
	327	"run scan_dev_for_boot; " \
	328	"fi; " \
	329	"done\0" \
b8ae6798 SG	330	"scan_dev_for_boot=" \
	331	"echo Scanning ${devtype} " \
	332	"${devnum}:${distro_bootpart}...; " \
	333	"for prefix in ${boot_prefixes}; do " \
	334	"run scan_dev_for_scripts; " \
	335	"done;" \
	336	"\0" \
	337	"boot_a_script=" \
	338	"load ${devtype} ${devnum}:${distro_bootpart} " \
	339	"${scriptaddr} ${prefix}${script}; " \
	340	"env exists secureboot && load ${devtype} " \
	341	"${devnum}:${distro_bootpart} " \
78c58082 VP	342	"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
78c58082 VP	343	"env exists secureboot " \
b8ae6798 SG	344	"&& esbc_validate ${scripthdraddr};" \
b8ae6798 SG	345	"source ${scriptaddr}\0" \
a65d7408 AW	346	"installer=load mmc 0:2 $load_addr " \
	347	"/flex_installer_arm32.itb; " \
	348	"bootm $load_addr#ls1021atwr\0" \
	349	"qspi_bootcmd=echo Trying load from qspi..;" \
	350	"sf probe && sf read $load_addr " \
	351	"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
	352	"nor_bootcmd=echo Trying load from nor..;" \
	353	"cp.b $kernel_addr $load_addr " \
	354	"$kernel_size && bootm $load_addr#$board\0"
55d53ab4	355	#else
c8a7d9da	356	#define CONFIG_EXTRA_ENV_SETTINGS \
33c3dfd2 AW	357	"bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
33c3dfd2 AW	358	"cma=64M@0x0-0xb0000000\0" \
7ff7166c	359	"initrd_high=0xffffffff\0" \
a65d7408	360	"fdt_addr=0x64f00000\0" \
9b457cc6 VPB	361	"kernel_addr=0x61000000\0" \
9b457cc6 VPB	362	"kernelheader_addr=0x60800000\0" \
a65d7408	363	"scriptaddr=0x80000000\0" \
b8ae6798	364	"scripthdraddr=0x80080000\0" \
a65d7408 AW	365	"fdtheader_addr_r=0x80100000\0" \
	366	"kernelheader_addr_r=0x80200000\0" \
	367	"kernel_addr_r=0x81000000\0" \
9b457cc6	368	"kernelheader_size=0x40000\0" \
a65d7408 AW	369	"fdt_addr_r=0x90000000\0" \
	370	"ramdisk_addr_r=0xa0000000\0" \
	371	"load_addr=0xa0000000\0" \
	372	"kernel_size=0x2800000\0" \
9b457cc6 VPB	373	"kernel_addr_sd=0x8000\0" \
	374	"kernel_size_sd=0x14000\0" \
	375	"kernelhdr_addr_sd=0x4000\0" \
	376	"kernelhdr_size_sd=0x10\0" \
feb8fa2e	377	"othbootargs=cma=64M@0x0-0xb0000000\0" \
a65d7408 AW	378	BOOTENV \
a65d7408 AW	379	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	380	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	381	"scan_dev_for_boot_part=" \
	382	"part list ${devtype} ${devnum} devplist; " \
	383	"env exists devplist \|\| setenv devplist 1; " \
	384	"for distro_bootpart in ${devplist}; do " \
	385	"if fstype ${devtype} " \
	386	"${devnum}:${distro_bootpart} " \
	387	"bootfstype; then " \
	388	"run scan_dev_for_boot; " \
	389	"fi; " \
	390	"done\0" \
b8ae6798 SG	391	"scan_dev_for_boot=" \
	392	"echo Scanning ${devtype} " \
	393	"${devnum}:${distro_bootpart}...; " \
	394	"for prefix in ${boot_prefixes}; do " \
	395	"run scan_dev_for_scripts; " \
	396	"done;" \
	397	"\0" \
	398	"boot_a_script=" \
	399	"load ${devtype} ${devnum}:${distro_bootpart} " \
	400	"${scriptaddr} ${prefix}${script}; " \
	401	"env exists secureboot && load ${devtype} " \
	402	"${devnum}:${distro_bootpart} " \
	403	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	404	"&& esbc_validate ${scripthdraddr};" \
	405	"source ${scriptaddr}\0" \
a65d7408 AW	406	"qspi_bootcmd=echo Trying load from qspi..;" \
a65d7408 AW	407	"sf probe && sf read $load_addr " \
9b457cc6 VPB	408	"$kernel_addr $kernel_size; env exists secureboot " \
	409	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	410	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	411	"bootm $load_addr#$board\0" \
a65d7408 AW	412	"nor_bootcmd=echo Trying load from nor..;" \
a65d7408 AW	413	"cp.b $kernel_addr $load_addr " \
9b457cc6 VPB	414	"$kernel_size; env exists secureboot " \
	415	"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
	416	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	417	"bootm $load_addr#$board\0" \
397a173e SL	418	"sd_bootcmd=echo Trying load from SD ..;" \
	419	"mmcinfo && mmc read $load_addr " \
	420	"$kernel_addr_sd $kernel_size_sd && " \
9b457cc6 VPB	421	"env exists secureboot && mmc read $kernelheader_addr_r " \
	422	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	423	" && esbc_validate ${kernelheader_addr_r};" \
397a173e	424	"bootm $load_addr#$board\0"
55d53ab4	425	#endif
c8a7d9da	426
a65d7408 AW	427	#undef CONFIG_BOOTCOMMAND
a65d7408 AW	428	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
c40e65eb	429	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
9b457cc6	430	"env exists secureboot && esbc_halt"
397a173e	431	#elif defined(CONFIG_SD_BOOT)
9b457cc6 VPB	432	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
9b457cc6 VPB	433	"env exists secureboot && esbc_halt;"
a65d7408	434	#else
9b457cc6 VPB	435	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \
9b457cc6 VPB	436	"env exists secureboot && esbc_halt;"
a65d7408 AW	437	#endif
a65d7408 AW	438
c8a7d9da WH	439	/*
	440	* Miscellaneous configurable options
	441	*/
c463eeb4	442	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
c8a7d9da	443
c8a7d9da	444	#define CONFIG_SYS_LOAD_ADDR 0x82000000
c8a7d9da	445
660673af XL	446	#define CONFIG_LS102XA_STREAM_ID
660673af XL	447
c8a7d9da WH	448	#define CONFIG_SYS_INIT_SP_OFFSET \
	449	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	450	#define CONFIG_SYS_INIT_SP_ADDR \
	451	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	452
8415bb68 AW	453	#ifdef CONFIG_SPL_BUILD
8415bb68 AW	454	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
9ebde884	455	#undef CONFIG_DM_I2C
8415bb68	456	#else
c8a7d9da	457	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
8415bb68	458	#endif
c8a7d9da	459
615bfce5	460	#define CONFIG_SYS_QE_FW_ADDR 0x60940000
eaa859e7	461
c8a7d9da WH	462	/*
	463	* Environment
	464	*/
	465	#define CONFIG_ENV_OVERWRITE
	466
8415bb68	467	#if defined(CONFIG_SD_BOOT)
8415bb68	468	#define CONFIG_SYS_MMC_ENV_DEV 0
8415bb68	469	#endif
c8a7d9da	470
ef6c55a2	471	#include <asm/fsl_secure_boot.h>
cc7b8b9a	472	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	473
c8a7d9da	474	#endif