[thirdparty/u-boot.git] / include / configs / ls1028aqds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2019-2020 NXP
 */

#ifndef __LS1028A_QDS_H
#define __LS1028A_QDS_H

#include "ls1028a_common.h"

#define COUNTER_FREQUENCY_REAL		(get_board_sys_clk() / 4)

/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR		2

#define CONFIG_QIXIS_I2C_ACCESS

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		1
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		5
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x00
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_EMMC		0x00
#define QIXIS_LBMAP_QSPI		0x00
#define QIXIS_RCW_SRC_SD		0x8
#define QIXIS_RCW_SRC_EMMC		0x9
#define QIXIS_RCW_SRC_QSPI		0xf
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)
#endif

/* RTC */
#define CONFIG_SYS_RTC_BUS_NUM         1
#define I2C_MUX_CH_RTC                 0xB

/* Store environment at top of flash */

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif

/* LPUART */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#define CFG_LPUART_MUX_MASK	0xf0
#define CFG_LPUART_EN		0xf0
#endif

/* SATA */
#define CONFIG_SCSI_AHCI_PLAT

#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#ifndef SPL_NO_ENV
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
	"board=ls1028aqds\0" \
	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	"ramdisk_addr=0x800000\0" \
	"ramdisk_size=0x2000000\0" \
	"fdt_addr=0x00f00000\0" \
	"kernel_addr=0x01000000\0" \
	"scriptaddr=0x80000000\0" \
	"scripthdraddr=0x80080000\0" \
	"fdtheader_addr_r=0x80100000\0" \
	"kernelheader_addr_r=0x80200000\0" \
	"load_addr=0xa0000000\0" \
	"kernel_addr_r=0x81000000\0" \
	"fdt_addr_r=0x90000000\0" \
	"fdt2_addr_r=0x90010000\0" \
	"ramdisk_addr_r=0xa0000000\0" \
	"kernel_start=0x1000000\0" \
	"kernelheader_start=0x600000\0" \
	"kernel_load=0xa0000000\0" \
	"kernel_size=0x2800000\0" \
	"kernelheader_size=0x40000\0" \
	"kernel_addr_sd=0x8000\0" \
	"kernel_size_sd=0x14000\0" \
	"kernelhdr_addr_sd=0x3000\0" \
	"kernelhdr_size_sd=0x10\0" \
	"console=ttyS0,115200\0" \
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	BOOTENV \
	"boot_scripts=ls1028aqds_boot.scr\0" \
	"boot_script_hdr=hdr_ls1028aqds_bs.out\0" \
	"scan_dev_for_boot_part=" \
		"part list ${devtype} ${devnum} devplist; " \
		"env exists devplist || setenv devplist 1; " \
		"for distro_bootpart in ${devplist}; do " \
		  "if fstype ${devtype} " \
			"${devnum}:${distro_bootpart} " \
			"bootfstype; then " \
			"run scan_dev_for_boot; " \
		  "fi; " \
		"done\0" \
	"boot_a_script=" \
		"load ${devtype} ${devnum}:${distro_bootpart} " \
			"${scriptaddr} ${prefix}${script}; " \
		"env exists secureboot && load ${devtype} " \
			"${devnum}:${distro_bootpart} " \
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};" \
		"source ${scriptaddr}\0" \
	"xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
		"sf probe 0:0 && sf read $load_addr " \
		"$kernel_start $kernel_size ; env exists secureboot &&" \
		"sf read $kernelheader_addr_r $kernelheader_start " \
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		" bootm $load_addr#$board\0" \
	"xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
		"sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \
		"&& hdp load $load_addr 0x2000\0"			\
	"sd_bootcmd=echo Trying load from SD ...;" \
		"mmc dev 0; mmcinfo; mmc read $load_addr "		\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r " \
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"		\
	"sd_hdploadcmd=echo Trying load HDP firmware from SD..;"        \
		"mmc dev 0;mmcinfo; mmc read $load_addr 0x4a00 0x200 "	\
		"&& hdp load $load_addr 0x2000\0"	\
	"emmc_bootcmd=echo Trying load from EMMC ..;"	\
		"mmc dev 1; mmcinfo; mmc read $load_addr "		\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r " \
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"			\
	"emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"      \
		"mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 "	\
		"&& hdp load $load_addr 0x2000\0"

#endif
#endif /* __LS1028A_QDS_H */
Commit	Line	Data
f278a217 YT	1	/* SPDX-License-Identifier: GPL-2.0+ */
f278a217 YT	2	/*
160e2b88	3	* Copyright 2019-2020 NXP
f278a217 YT	4	*/
	5
	6	#ifndef __LS1028A_QDS_H
	7	#define __LS1028A_QDS_H
	8
	9	#include "ls1028a_common.h"
	10
2f8a6db5	11	#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
f278a217 YT	12
	13	/* DDR */
	14	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	15
	16	#define CONFIG_QIXIS_I2C_ACCESS
f278a217 YT	17
	18	/*
	19	* QIXIS Definitions
	20	*/
	21	#define CONFIG_FSL_QIXIS
	22
	23	#ifdef CONFIG_FSL_QIXIS
	24	#define QIXIS_BASE 0x7fb00000
	25	#define QIXIS_BASE_PHYS QIXIS_BASE
	26	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	27	#define QIXIS_LBMAP_SWITCH 1
	28	#define QIXIS_LBMAP_MASK 0x0f
	29	#define QIXIS_LBMAP_SHIFT 5
	30	#define QIXIS_LBMAP_DFLTBANK 0x00
	31	#define QIXIS_LBMAP_ALTBANK 0x00
	32	#define QIXIS_LBMAP_SD 0x00
	33	#define QIXIS_LBMAP_EMMC 0x00
	34	#define QIXIS_LBMAP_QSPI 0x00
	35	#define QIXIS_RCW_SRC_SD 0x8
	36	#define QIXIS_RCW_SRC_EMMC 0x9
	37	#define QIXIS_RCW_SRC_QSPI 0xf
	38	#define QIXIS_RST_CTL_RESET 0x31
	39	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	40	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	41	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	42	#define QIXIS_RST_FORCE_MEM 0x01
	43
	44	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	45	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
	46	CSPR_PORT_SIZE_8 \| \
	47	CSPR_MSEL_GPCM \| \
	48	CSPR_V)
	49	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	50	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	51	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	52	CSOR_NOR_TRHZ_80)
	53	#endif
	54
	55	/* RTC */
	56	#define CONFIG_SYS_RTC_BUS_NUM 1
	57	#define I2C_MUX_CH_RTC 0xB
	58
	59	/* Store environment at top of flash */
f278a217 YT	60
	61	#ifdef CONFIG_SPL_BUILD
	62	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	63	#else
	64	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	65	#endif
	66
7dfa44f7 YT	67	/* LPUART */
	68	#ifdef CONFIG_LPUART
	69	#define CONFIG_LPUART_32B_REG
	70	#define CFG_LPUART_MUX_MASK 0xf0
	71	#define CFG_LPUART_EN 0xf0
	72	#endif
	73
f278a217 YT	74	/* SATA */
	75	#define CONFIG_SCSI_AHCI_PLAT
	76
	77	#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
f278a217 YT	78	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
f278a217 YT	79	#define CONFIG_SYS_SCSI_MAX_LUN 1
f278a217 YT	80	#ifndef SPL_NO_ENV
	81	#undef CONFIG_EXTRA_ENV_SETTINGS
	82	#define CONFIG_EXTRA_ENV_SETTINGS \
	83	"board=ls1028aqds\0" \
	84	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	85	"ramdisk_addr=0x800000\0" \
	86	"ramdisk_size=0x2000000\0" \
f278a217 YT	87	"fdt_addr=0x00f00000\0" \
	88	"kernel_addr=0x01000000\0" \
	89	"scriptaddr=0x80000000\0" \
	90	"scripthdraddr=0x80080000\0" \
	91	"fdtheader_addr_r=0x80100000\0" \
	92	"kernelheader_addr_r=0x80200000\0" \
	93	"load_addr=0xa0000000\0" \
	94	"kernel_addr_r=0x81000000\0" \
	95	"fdt_addr_r=0x90000000\0" \
40ef9d16	96	"fdt2_addr_r=0x90010000\0" \
f278a217 YT	97	"ramdisk_addr_r=0xa0000000\0" \
f278a217 YT	98	"kernel_start=0x1000000\0" \
160e2b88	99	"kernelheader_start=0x600000\0" \
f278a217 YT	100	"kernel_load=0xa0000000\0" \
	101	"kernel_size=0x2800000\0" \
	102	"kernelheader_size=0x40000\0" \
	103	"kernel_addr_sd=0x8000\0" \
	104	"kernel_size_sd=0x14000\0" \
160e2b88	105	"kernelhdr_addr_sd=0x3000\0" \
f278a217 YT	106	"kernelhdr_size_sd=0x10\0" \
	107	"console=ttyS0,115200\0" \
	108	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	109	BOOTENV \
	110	"boot_scripts=ls1028aqds_boot.scr\0" \
	111	"boot_script_hdr=hdr_ls1028aqds_bs.out\0" \
	112	"scan_dev_for_boot_part=" \
	113	"part list ${devtype} ${devnum} devplist; " \
	114	"env exists devplist \|\| setenv devplist 1; " \
	115	"for distro_bootpart in ${devplist}; do " \
	116	"if fstype ${devtype} " \
	117	"${devnum}:${distro_bootpart} " \
	118	"bootfstype; then " \
	119	"run scan_dev_for_boot; " \
	120	"fi; " \
	121	"done\0" \
f278a217 YT	122	"boot_a_script=" \
	123	"load ${devtype} ${devnum}:${distro_bootpart} " \
	124	"${scriptaddr} ${prefix}${script}; " \
	125	"env exists secureboot && load ${devtype} " \
	126	"${devnum}:${distro_bootpart} " \
	127	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	128	"&& esbc_validate ${scripthdraddr};" \
	129	"source ${scriptaddr}\0" \
40ef9d16 YT	130	"xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
	131	"sf probe 0:0 && sf read $load_addr " \
	132	"$kernel_start $kernel_size ; env exists secureboot &&" \
	133	"sf read $kernelheader_addr_r $kernelheader_start " \
	134	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
	135	" bootm $load_addr#$board\0" \
	136	"xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
	137	"sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \
	138	"&& hdp load $load_addr 0x2000\0" \
	139	"sd_bootcmd=echo Trying load from SD ...;" \
	140	"mmc dev 0; mmcinfo; mmc read $load_addr " \
	141	"$kernel_addr_sd $kernel_size_sd && " \
f278a217	142	"env exists secureboot && mmc read $kernelheader_addr_r " \
40ef9d16 YT	143	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	144	" && esbc_validate ${kernelheader_addr_r};" \
	145	"bootm $load_addr#$board\0" \
	146	"sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \
	147	"mmc dev 0;mmcinfo; mmc read $load_addr 0x4a00 0x200 " \
	148	"&& hdp load $load_addr 0x2000\0" \
	149	"emmc_bootcmd=echo Trying load from EMMC ..;" \
	150	"mmc dev 1; mmcinfo; mmc read $load_addr " \
	151	"$kernel_addr_sd $kernel_size_sd && " \
f278a217	152	"env exists secureboot && mmc read $kernelheader_addr_r " \
40ef9d16	153	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
f278a217	154	" && esbc_validate ${kernelheader_addr_r};" \
40ef9d16 YT	155	"bootm $load_addr#$board\0" \
	156	"emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \
	157	"mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
	158	"&& hdp load $load_addr 0x2000\0"
	159
f278a217 YT	160	#endif
f278a217 YT	161	#endif /* __LS1028A_QDS_H */