[thirdparty/u-boot.git] / include / configs / ls1028ardb.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2019, 2021 NXP
 */

#ifndef __LS1028A_RDB_H
#define __LS1028A_RDB_H

#include "ls1028a_common.h"

#define COUNTER_FREQUENCY_REAL		(get_board_sys_clk() / 4)

#define CFG_SYS_RTC_BUS_NUM         0

/* Store environment at top of flash */

/*
 * QIXIS Definitions
 */

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CFG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		2
#define QIXIS_LBMAP_MASK		0xe0
#define QIXIS_LBMAP_SHIFT		0x5
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x00
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_EMMC		0x00
#define QIXIS_LBMAP_XSPI		0x00
#define QIXIS_RCW_SRC_SD		0xf8
#define QIXIS_RCW_SRC_EMMC		0xf9
#define QIXIS_RCW_SRC_XSPI		0xff
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x10
#define QIXIS_RCFG_CTL_RECONFIG_START	0x11
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RST_FORCE_MEM		0x01

#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CFG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)
#endif

/* Initial environment variables */
#ifndef SPL_NO_ENV
#undef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS		\
	"board=ls1028ardb\0"			\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"bootm_size=0x10000000\0"		\
	"kernel_addr=0x01000000\0"              \
	"scriptaddr=0x80000000\0"               \
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"         \
	"kernelheader_addr_r=0x80200000\0"      \
	"load_addr=0xa0000000\0"            \
	"kernel_addr_r=0x81000000\0"            \
	"fdt_addr_r=0x90000000\0"               \
	"ramdisk_addr_r=0xa0000000\0"           \
	"kernel_start=0x1000000\0"		\
	"kernelheader_start=0x600000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"kernelheader_size=0x40000\0"		\
	"kernel_addr_sd=0x8000\0"		\
	"kernel_size_sd=0x14000\0"		\
	"kernelhdr_addr_sd=0x3000\0"		\
	"kernelhdr_size_sd=0x20\0"		\
	"console=ttyS0,115200\0"                \
	BOOTENV					\
	"boot_scripts=ls1028ardb_boot.scr\0"    \
	"boot_script_hdr=hdr_ls1028ardb_bs.out\0"	\
	"scan_dev_for_boot_part="               \
		"part list ${devtype} ${devnum} devplist; "   \
		"env exists devplist || setenv devplist 1; "  \
		"for distro_bootpart in ${devplist}; do "     \
		  "if fstype ${devtype} "                  \
			"${devnum}:${distro_bootpart} "      \
			"bootfstype; then "                  \
			"run scan_dev_for_boot; "            \
		  "fi; "                                   \
		"done\0"                                   \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
		"sf probe 0:0 && sf read $load_addr " \
		"$kernel_start $kernel_size ; env exists secureboot &&" \
		"sf read $kernelheader_addr_r $kernelheader_start " \
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		" bootm $load_addr#$board\0" \
	"xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
		"sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \
		"&& hdp load $load_addr 0x2000\0"			\
	"sd_bootcmd=echo Trying load from SD ...;" \
		"mmc dev 0;mmcinfo; mmc read $load_addr "		\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r " \
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"		\
	"sd_hdploadcmd=echo Trying load HDP firmware from SD..;"	\
		"mmc dev 0;mmcinfo;mmc read $load_addr 0x4a00 0x200 "	\
		"&& hdp load $load_addr 0x2000\0"	\
	"emmc_bootcmd=echo Trying load from EMMC ..;"	\
		"mmc dev 1;mmcinfo; mmc read $load_addr "		\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r " \
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"			\
	"emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;"      \
		"mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 "	\
		"&& hdp load $load_addr 0x2000\0"
#endif
#endif /* __LS1028A_RDB_H */
Commit	Line	Data
353f36d9 YT	1	/* SPDX-License-Identifier: GPL-2.0+ */
353f36d9 YT	2	/*
b416df33	3	* Copyright 2019, 2021 NXP
353f36d9 YT	4	*/
	5
	6	#ifndef __LS1028A_RDB_H
	7	#define __LS1028A_RDB_H
	8
	9	#include "ls1028a_common.h"
	10
2f8a6db5	11	#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
353f36d9	12
65cc0e2a	13	#define CFG_SYS_RTC_BUS_NUM 0
353f36d9 YT	14
353f36d9 YT	15	/* Store environment at top of flash */
353f36d9	16
353f36d9 YT	17	/*
	18	* QIXIS Definitions
	19	*/
353f36d9 YT	20
	21	#ifdef CONFIG_FSL_QIXIS
	22	#define QIXIS_BASE 0x7fb00000
	23	#define QIXIS_BASE_PHYS QIXIS_BASE
65cc0e2a	24	#define CFG_SYS_I2C_FPGA_ADDR 0x66
353f36d9 YT	25	#define QIXIS_LBMAP_SWITCH 2
	26	#define QIXIS_LBMAP_MASK 0xe0
	27	#define QIXIS_LBMAP_SHIFT 0x5
	28	#define QIXIS_LBMAP_DFLTBANK 0x00
	29	#define QIXIS_LBMAP_ALTBANK 0x00
	30	#define QIXIS_LBMAP_SD 0x00
	31	#define QIXIS_LBMAP_EMMC 0x00
c8f8830e	32	#define QIXIS_LBMAP_XSPI 0x00
353f36d9 YT	33	#define QIXIS_RCW_SRC_SD 0xf8
353f36d9 YT	34	#define QIXIS_RCW_SRC_EMMC 0xf9
c8f8830e	35	#define QIXIS_RCW_SRC_XSPI 0xff
353f36d9 YT	36	#define QIXIS_RST_CTL_RESET 0x31
	37	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10
	38	#define QIXIS_RCFG_CTL_RECONFIG_START 0x11
	39	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	40	#define QIXIS_RST_FORCE_MEM 0x01
	41
65cc0e2a TR	42	#define CFG_SYS_FPGA_CSPR_EXT (0x0)
65cc0e2a TR	43	#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
353f36d9 YT	44	CSPR_PORT_SIZE_8 \| \
	45	CSPR_MSEL_GPCM \| \
	46	CSPR_V)
65cc0e2a	47	#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
353f36d9 YT	48	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	49	CSOR_NOR_TRHZ_80)
	50	#endif
	51
a023c3c2 YT	52	/* Initial environment variables */
a023c3c2 YT	53	#ifndef SPL_NO_ENV
0613c36a TR	54	#undef CFG_EXTRA_ENV_SETTINGS
0613c36a TR	55	#define CFG_EXTRA_ENV_SETTINGS \
a023c3c2 YT	56	"board=ls1028ardb\0" \
	57	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	58	"ramdisk_addr=0x800000\0" \
	59	"ramdisk_size=0x2000000\0" \
	60	"bootm_size=0x10000000\0" \
a023c3c2 YT	61	"kernel_addr=0x01000000\0" \
	62	"scriptaddr=0x80000000\0" \
	63	"scripthdraddr=0x80080000\0" \
	64	"fdtheader_addr_r=0x80100000\0" \
	65	"kernelheader_addr_r=0x80200000\0" \
	66	"load_addr=0xa0000000\0" \
	67	"kernel_addr_r=0x81000000\0" \
	68	"fdt_addr_r=0x90000000\0" \
	69	"ramdisk_addr_r=0xa0000000\0" \
	70	"kernel_start=0x1000000\0" \
	71	"kernelheader_start=0x600000\0" \
	72	"kernel_load=0xa0000000\0" \
	73	"kernel_size=0x2800000\0" \
	74	"kernelheader_size=0x40000\0" \
	75	"kernel_addr_sd=0x8000\0" \
	76	"kernel_size_sd=0x14000\0" \
	77	"kernelhdr_addr_sd=0x3000\0" \
	78	"kernelhdr_size_sd=0x20\0" \
	79	"console=ttyS0,115200\0" \
a023c3c2 YT	80	BOOTENV \
	81	"boot_scripts=ls1028ardb_boot.scr\0" \
	82	"boot_script_hdr=hdr_ls1028ardb_bs.out\0" \
	83	"scan_dev_for_boot_part=" \
	84	"part list ${devtype} ${devnum} devplist; " \
	85	"env exists devplist \|\| setenv devplist 1; " \
	86	"for distro_bootpart in ${devplist}; do " \
	87	"if fstype ${devtype} " \
	88	"${devnum}:${distro_bootpart} " \
	89	"bootfstype; then " \
	90	"run scan_dev_for_boot; " \
	91	"fi; " \
	92	"done\0" \
a023c3c2 YT	93	"boot_a_script=" \
	94	"load ${devtype} ${devnum}:${distro_bootpart} " \
	95	"${scriptaddr} ${prefix}${script}; " \
	96	"env exists secureboot && load ${devtype} " \
	97	"${devnum}:${distro_bootpart} " \
	98	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	99	"&& esbc_validate ${scripthdraddr};" \
	100	"source ${scriptaddr}\0" \
	101	"xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
	102	"sf probe 0:0 && sf read $load_addr " \
	103	"$kernel_start $kernel_size ; env exists secureboot &&" \
	104	"sf read $kernelheader_addr_r $kernelheader_start " \
	105	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
	106	" bootm $load_addr#$board\0" \
	107	"xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
	108	"sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \
	109	"&& hdp load $load_addr 0x2000\0" \
	110	"sd_bootcmd=echo Trying load from SD ...;" \
	111	"mmc dev 0;mmcinfo; mmc read $load_addr " \
	112	"$kernel_addr_sd $kernel_size_sd && " \
	113	"env exists secureboot && mmc read $kernelheader_addr_r " \
	114	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	115	" && esbc_validate ${kernelheader_addr_r};" \
	116	"bootm $load_addr#$board\0" \
	117	"sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \
	118	"mmc dev 0;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
	119	"&& hdp load $load_addr 0x2000\0" \
	120	"emmc_bootcmd=echo Trying load from EMMC ..;" \
	121	"mmc dev 1;mmcinfo; mmc read $load_addr " \
	122	"$kernel_addr_sd $kernel_size_sd && " \
	123	"env exists secureboot && mmc read $kernelheader_addr_r " \
	124	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	125	" && esbc_validate ${kernelheader_addr_r};" \
	126	"bootm $load_addr#$board\0" \
	127	"emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \
	128	"mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
	129	"&& hdp load $load_addr 0x2000\0"
	130	#endif
353f36d9	131	#endif /* __LS1028A_RDB_H */