[thirdparty/u-boot.git] / include / configs / ls1043ardb.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2015 Freescale Semiconductor
 */

#ifndef __LS1043ARDB_H__
#define __LS1043ARDB_H__

#include "ls1043a_common.h"

#define CONFIG_LAYERSCAPE_NS_ACCESS

/* Physical Memory Map */

#define CONFIG_SYS_SPD_BUS_NUM		0

#ifndef CONFIG_SPL
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_SPL_ARGS_ADDR	0x90000000
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x500
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	30
#endif

/*
 * NOR Flash Definitions
 */
#define CONFIG_SYS_NOR_CSPR_EXT		(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
					FTIM0_NOR_TEADC(0x1) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0xc))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1c) | \
					FTIM1_NOR_TRAD_NOR(0xb) | \
					FTIM1_NOR_TSEQRAD_NOR(0x9))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0x8) | \
					FTIM2_NOR_TWP(0x10))
#define CONFIG_SYS_NOR_FTIM3		0
#define CONFIG_SYS_IFC_CCR		0x01000000

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_SYS_WRITE_SWAPPED_DATA

/*
 * NAND Flash Definitions
 */

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1024 << 10)
#endif

/*
 * CPLD
 */
#define CONFIG_SYS_CPLD_BASE		0x7fb00000
#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CPLD_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_CPLD_FTIM3		0x0

/* IFC Timing Params */
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3

#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#else
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3

#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif
#endif

#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3

/* EEPROM */
#ifndef SPL_NO_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0
#endif

/*
 * Environment
 */

/* FMan */
#ifndef SPL_NO_FMAN
#define AQR105_IRQ_MASK			0x40000000

#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR			0x1
#define RGMII_PHY2_ADDR			0x2

#define QSGMII_PORT1_PHY_ADDR		0x4
#define QSGMII_PORT2_PHY_ADDR		0x5
#define QSGMII_PORT3_PHY_ADDR		0x6
#define QSGMII_PORT4_PHY_ADDR		0x7

#define FM1_10GEC1_PHY_ADDR		0x1
#endif
#endif

/* SATA */
#ifndef SPL_NO_SATA
#define SCSI_VEND_ID 0x1b4b
#define SCSI_DEV_ID  0x9170
#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS1043ARDB_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
f3a8e2b7 MH	2	/*
f3a8e2b7 MH	3	* Copyright 2015 Freescale Semiconductor
f3a8e2b7 MH	4	*/
	5
	6	#ifndef __LS1043ARDB_H__
	7	#define __LS1043ARDB_H__
	8
	9	#include "ls1043a_common.h"
	10
f3a8e2b7	11	#define CONFIG_LAYERSCAPE_NS_ACCESS
f3a8e2b7	12
f3a8e2b7	13	/* Physical Memory Map */
f3a8e2b7 MH	14
	15	#define CONFIG_SYS_SPD_BUS_NUM 0
	16
dc760aed	17	#ifndef CONFIG_SPL
f3a8e2b7	18	#define CONFIG_SYS_DDR_RAW_TIMING
f3a8e2b7	19	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
f554411b	20	#endif
f3a8e2b7	21
c7ca8b07	22	#ifdef CONFIG_SD_BOOT
23af484b	23	#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
23af484b YS	24	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
23af484b YS	25	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
c7ca8b07 GQ	26	#endif
c7ca8b07 GQ	27
f3a8e2b7 MH	28	/*
	29	* NOR Flash Definitions
	30	*/
	31	#define CONFIG_SYS_NOR_CSPR_EXT (0x0)
	32	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	33	#define CONFIG_SYS_NOR_CSPR \
	34	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	35	CSPR_PORT_SIZE_16 \| \
	36	CSPR_MSEL_NOR \| \
	37	CSPR_V)
	38
	39	/* NOR Flash Timing Params */
	40	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	41	CSOR_NOR_TRHZ_80)
	42	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) \| \
	43	FTIM0_NOR_TEADC(0x1) \| \
	44	FTIM0_NOR_TAVDS(0x0) \| \
	45	FTIM0_NOR_TEAHC(0xc))
	46	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) \| \
	47	FTIM1_NOR_TRAD_NOR(0xb) \| \
	48	FTIM1_NOR_TSEQRAD_NOR(0x9))
	49	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \| \
	50	FTIM2_NOR_TCH(0x4) \| \
	51	FTIM2_NOR_TWPH(0x8) \| \
	52	FTIM2_NOR_TWP(0x10))
	53	#define CONFIG_SYS_NOR_FTIM3 0
	54	#define CONFIG_SYS_IFC_CCR 0x01000000
	55
f3a8e2b7 MH	56	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	57	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	58	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	59
	60	#define CONFIG_SYS_FLASH_EMPTY_INFO
	61	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	62
f3a8e2b7 MH	63	#define CONFIG_SYS_WRITE_SWAPPED_DATA
	64
	65	/*
	66	* NAND Flash Definitions
	67	*/
f3a8e2b7 MH	68
	69	#define CONFIG_SYS_NAND_BASE 0x7e800000
	70	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	71
	72	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	73	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	74	\| CSPR_PORT_SIZE_8 \
	75	\| CSPR_MSEL_NAND \
	76	\| CSPR_V)
	77	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	78	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	79	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	80	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	81	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	82	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	83	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	84	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	85
f3a8e2b7 MH	86	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	87	FTIM0_NAND_TWP(0x18) \| \
	88	FTIM0_NAND_TWCHT(0x7) \| \
	89	FTIM0_NAND_TWH(0xa))
	90	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	91	FTIM1_NAND_TWBE(0x39) \| \
	92	FTIM1_NAND_TRR(0xe) \| \
	93	FTIM1_NAND_TRP(0x18))
	94	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	95	FTIM2_NAND_TREH(0xa) \| \
	96	FTIM2_NAND_TWHRE(0x1e))
	97	#define CONFIG_SYS_NAND_FTIM3 0x0
	98
	99	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	100	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	101	#define CONFIG_MTD_NAND_VERIFY_WRITE
f3a8e2b7	102
3ad44729	103	#ifdef CONFIG_NAND_BOOT
762f92a6	104	#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
3ad44729 GQ	105	#endif
3ad44729 GQ	106
f3a8e2b7 MH	107	/*
	108	* CPLD
	109	*/
	110	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	111	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	112
	113	#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
	114	#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	115	CSPR_PORT_SIZE_8 \| \
	116	CSPR_MSEL_GPCM \| \
	117	CSPR_V)
	118	#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
	119	#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	120	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	121	CSOR_NOR_TRHZ_80)
	122
	123	/* CPLD Timing parameters for IFC GPCM */
	124	#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	125	FTIM0_GPCM_TEADC(0xf) \| \
	126	FTIM0_GPCM_TEAHC(0xf))
	127	#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	128	FTIM1_GPCM_TRAD(0x3f))
	129	#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	130	FTIM2_GPCM_TCH(0xf) \| \
	131	FTIM2_GPCM_TWP(0xff))
	132	#define CONFIG_SYS_CPLD_FTIM3 0x0
	133
	134	/* IFC Timing Params */
f71b5f11 RB	135	#ifdef CONFIG_TFABOOT
	136	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
	137	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
	138	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	139	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	140	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	141	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	142	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	143	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	144
	145	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	146	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	147	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	148	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	149	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	150	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	151	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	152	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
	153	#else
3ad44729 GQ	154	#ifdef CONFIG_NAND_BOOT
	155	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	156	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	157	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	158	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	159	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	160	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	161	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	162	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	163
	164	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
	165	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
	166	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	167	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	168	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	169	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	170	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	171	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	172	#else
f3a8e2b7 MH	173	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
	174	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
	175	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	176	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	177	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	178	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	179	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	180	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	181
	182	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	183	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	184	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	185	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	186	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	187	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	188	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	189	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
3ad44729	190	#endif
f71b5f11	191	#endif
f3a8e2b7 MH	192
	193	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
	194	#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
	195	#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
	196	#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
	197	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
	198	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
	199	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
	200	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
	201
	202	/* EEPROM */
4139b170	203	#ifndef SPL_NO_EEPROM
f3a8e2b7 MH	204	#define CONFIG_SYS_I2C_EEPROM_NXID
f3a8e2b7 MH	205	#define CONFIG_SYS_EEPROM_BUS_NUM 0
4139b170	206	#endif
f3a8e2b7 MH	207
	208	/*
	209	* Environment
	210	*/
3ad44729	211
e8297341	212	/* FMan */
4139b170	213	#ifndef SPL_NO_FMAN
c40e6f91 YS	214	#define AQR105_IRQ_MASK 0x40000000
c40e6f91 YS	215
c40e6f91	216	#ifdef CONFIG_SYS_DPAA_FMAN
e8297341 SX	217	#define RGMII_PHY1_ADDR 0x1
	218	#define RGMII_PHY2_ADDR 0x2
	219
	220	#define QSGMII_PORT1_PHY_ADDR 0x4
	221	#define QSGMII_PORT2_PHY_ADDR 0x5
	222	#define QSGMII_PORT3_PHY_ADDR 0x6
	223	#define QSGMII_PORT4_PHY_ADDR 0x7
	224
	225	#define FM1_10GEC1_PHY_ADDR 0x1
e8297341	226	#endif
4139b170	227	#endif
e8297341	228
bc323b3f	229	/* SATA */
4139b170	230	#ifndef SPL_NO_SATA
bc323b3f PL	231	#define SCSI_VEND_ID 0x1b4b
	232	#define SCSI_DEV_ID 0x9170
	233	#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
4139b170	234	#endif
bc323b3f	235
9711f528 AB	236	#include <asm/fsl_secure_boot.h>
9711f528 AB	237
f3a8e2b7	238	#endif /* __LS1043ARDB_H__ */