[people/ms/u-boot.git] / include / configs / ls1046a_common.h

/*
 * Copyright 2016 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1046A_COMMON_H
#define __LS1046A_COMMON_H

/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_QBMAN
#define SPL_NO_FMAN
#define SPL_NO_ENV
#define SPL_NO_MISC
#define SPL_NO_QSPI
#define SPL_NO_USB
#define SPL_NO_SATA
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#define SPL_NO_MMC
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
#define SPL_NO_IFC
#endif

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP
#define CONFIG_GICV2

#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_func

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT

#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1f000		/* 124 KiB */
#define CONFIG_SPL_STACK		0x10020000
#define CONFIG_SPL_PAD_TO		0x21000		/* 132 KiB */
#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT

#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x17000		/* 90 KiB */
#define CONFIG_SPL_STACK		0x1001f000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SYS_MONITOR_LEN		0xa0000
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4

/* Command line configuration */
#ifndef SPL_NO_ENV
#define CONFIG_CMD_ENV
#endif

/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif

#ifndef SPL_NO_QBMAN
#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
#endif

/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
#endif

#ifdef CONFIG_SD_BOOT
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x40300000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR		(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#ifndef SPL_NO_MISC
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x1000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyS0,115200\0"                \
		MTDPARTS_DEFAULT "\0"

#define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
					"earlycon=uart8250,mmio,0x21c0500 " \
					MTDPARTS_DEFAULT
#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP

#ifndef SPL_NO_MISC
#define CONFIG_CMDLINE_EDITING		1
#endif

#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

#endif /* __LS1046A_COMMON_H */
Commit	Line	Data
dd02936f MH	1	/*
	2	* Copyright 2016 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1046A_COMMON_H
	8	#define __LS1046A_COMMON_H
	9
a52ff334 SG	10	/* SPL build */
	11	#ifdef CONFIG_SPL_BUILD
	12	#define SPL_NO_QBMAN
	13	#define SPL_NO_FMAN
	14	#define SPL_NO_ENV
	15	#define SPL_NO_MISC
	16	#define SPL_NO_QSPI
	17	#define SPL_NO_USB
	18	#define SPL_NO_SATA
	19	#endif
	20	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
	21	#define SPL_NO_MMC
	22	#endif
	23	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
	24	#define SPL_NO_IFC
	25	#endif
	26
dd02936f MH	27	#define CONFIG_REMAKE_ELF
dd02936f MH	28	#define CONFIG_FSL_LAYERSCAPE
dd02936f	29	#define CONFIG_MP
dd02936f MH	30	#define CONFIG_GICV2
	31
	32	#include <asm/arch/config.h>
b52a0507	33	#include <asm/arch/stream_id_lsch2.h>
dd02936f MH	34
	35	/* Link Definitions */
	36	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	37
	38	#define CONFIG_SUPPORT_RAW_INITRD
	39
	40	#define CONFIG_SKIP_LOWLEVEL_INIT
dd02936f MH	41
	42	#define CONFIG_VERY_BIG_RAM
	43	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	44	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	45	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	46	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
	47
	48	#define CPU_RELEASE_ADDR secondary_boot_func
	49
	50	/* Generic Timer Definitions */
	51	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	52
	53	/* Size of malloc() pool */
	54	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	55
	56	/* Serial Port */
	57	#define CONFIG_CONS_INDEX 1
	58	#define CONFIG_SYS_NS16550_SERIAL
	59	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	60	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
dd02936f	61
dd02936f MH	62	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	63
	64	/* SD boot SPL */
	65	#ifdef CONFIG_SD_BOOT
	66	#define CONFIG_SPL_FRAMEWORK
	67	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	68	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	69	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	70	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	71	#define CONFIG_SPL_ENV_SUPPORT
	72	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	73	#define CONFIG_SPL_WATCHDOG_SUPPORT
	74	#define CONFIG_SPL_I2C_SUPPORT
	75	#define CONFIG_SPL_SERIAL_SUPPORT
	76	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	77
	78	#define CONFIG_SPL_MMC_SUPPORT
dd02936f MH	79	#define CONFIG_SPL_TEXT_BASE 0x10000000
	80	#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
	81	#define CONFIG_SPL_STACK 0x10020000
	82	#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
	83	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
	84	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	85	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	86	CONFIG_SPL_BSS_MAX_SIZE)
	87	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
511fc86d RG	88
	89	#ifdef CONFIG_SECURE_BOOT
	90	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	91	/*
	92	* HDR would be appended at end of image and copied to DDR along
	93	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	94	* size increases then increase this size in case of secure boot as
	95	* it uses raw u-boot image instead of fit image.
	96	*/
	97	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	98	#else
	99	#define CONFIG_SYS_MONITOR_LEN 0x100000
	100	#endif /* ifdef CONFIG_SECURE_BOOT */
dd02936f MH	101	#endif
dd02936f MH	102
126fe70d SX	103	/* NAND SPL */
	104	#ifdef CONFIG_NAND_BOOT
	105	#define CONFIG_SPL_PBL_PAD
	106	#define CONFIG_SPL_FRAMEWORK
	107	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	108	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	109	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	110	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	111	#define CONFIG_SPL_ENV_SUPPORT
	112	#define CONFIG_SPL_WATCHDOG_SUPPORT
	113	#define CONFIG_SPL_I2C_SUPPORT
	114	#define CONFIG_SPL_SERIAL_SUPPORT
	115	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	116
	117	#define CONFIG_SPL_NAND_SUPPORT
	118	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	119	#define CONFIG_SPL_TEXT_BASE 0x10000000
511fc86d	120	#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
126fe70d SX	121	#define CONFIG_SPL_STACK 0x1001f000
	122	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	123	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	124
	125	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
	126	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	127	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	128	CONFIG_SPL_BSS_MAX_SIZE)
	129	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	130	#define CONFIG_SYS_MONITOR_LEN 0xa0000
	131	#endif
	132
dd02936f MH	133	/* I2C */
	134	#define CONFIG_SYS_I2C
	135	#define CONFIG_SYS_I2C_MXC
	136	#define CONFIG_SYS_I2C_MXC_I2C1
	137	#define CONFIG_SYS_I2C_MXC_I2C2
	138	#define CONFIG_SYS_I2C_MXC_I2C3
	139	#define CONFIG_SYS_I2C_MXC_I2C4
	140
	141	/* Command line configuration */
a52ff334	142	#ifndef SPL_NO_ENV
dd02936f	143	#define CONFIG_CMD_ENV
a52ff334	144	#endif
dd02936f MH	145
dd02936f MH	146	/* MMC */
a52ff334	147	#ifndef SPL_NO_MMC
dd02936f MH	148	#ifdef CONFIG_MMC
	149	#define CONFIG_FSL_ESDHC
	150	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
dd02936f	151	#endif
a52ff334	152	#endif
dd02936f	153
a52ff334	154	#ifndef SPL_NO_QBMAN
dd02936f	155	#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
a52ff334	156	#endif
dd02936f MH	157
dd02936f MH	158	/* FMan ucode */
a52ff334	159	#ifndef SPL_NO_FMAN
dd02936f MH	160	#define CONFIG_SYS_DPAA_FMAN
	161	#ifdef CONFIG_SYS_DPAA_FMAN
	162	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
a52ff334	163	#endif
dd02936f MH	164
	165	#ifdef CONFIG_SD_BOOT
	166	/*
	167	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
	168	* about 1MB (2048 blocks), Env is stored after the image, and the env size is
	169	* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
	170	*/
	171	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
	172	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
126fe70d	173	#elif defined(CONFIG_QSPI_BOOT)
dd02936f MH	174	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
	175	#define CONFIG_SYS_FMAN_FW_ADDR 0x40300000
	176	#define CONFIG_ENV_SPI_BUS 0
	177	#define CONFIG_ENV_SPI_CS 0
	178	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	179	#define CONFIG_ENV_SPI_MODE 0x03
126fe70d SX	180	#elif defined(CONFIG_NAND_BOOT)
	181	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
	182	#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
	183	#else
	184	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
	185	#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
dd02936f MH	186	#endif
	187	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	188	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	189	#endif
	190
	191	/* Miscellaneous configurable options */
	192	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
dd02936f MH	193
	194	#define CONFIG_HWCONFIG
	195	#define HWCONFIG_BUFFER_SIZE 128
	196
a52ff334	197	#ifndef SPL_NO_MISC
dd02936f MH	198	/* Initial environment variables */
	199	#define CONFIG_EXTRA_ENV_SETTINGS \
	200	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	201	"loadaddr=0x80100000\0" \
	202	"ramdisk_addr=0x800000\0" \
	203	"ramdisk_size=0x2000000\0" \
	204	"fdt_high=0xffffffffffffffff\0" \
	205	"initrd_high=0xffffffffffffffff\0" \
	206	"kernel_start=0x1000000\0" \
	207	"kernel_load=0xa0000000\0" \
	208	"kernel_size=0x2800000\0" \
	209	"console=ttyS0,115200\0" \
	210	MTDPARTS_DEFAULT "\0"
	211
	212	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
	213	"earlycon=uart8250,mmio,0x21c0500 " \
	214	MTDPARTS_DEFAULT
a52ff334 SG	215	#endif
a52ff334 SG	216
dd02936f MH	217	/* Monitor Command Prompt */
	218	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	219	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	220	sizeof(CONFIG_SYS_PROMPT) + 16)
	221	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	222	#define CONFIG_SYS_LONGHELP
a52ff334 SG	223
a52ff334 SG	224	#ifndef SPL_NO_MISC
dd02936f	225	#define CONFIG_CMDLINE_EDITING 1
a52ff334 SG	226	#endif
a52ff334 SG	227
dd02936f MH	228	#define CONFIG_AUTO_COMPLETE
	229	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	230
	231	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	232
	233	/* Hash command with SHA acceleration supported in hardware */
	234	#ifdef CONFIG_FSL_CAAM
	235	#define CONFIG_CMD_HASH
	236	#define CONFIG_SHA_HW_ACCEL
	237	#endif
	238
	239	#endif /* __LS1046A_COMMON_H */