[people/ms/u-boot.git] / include / configs / ls1046a_common.h

/*
 * Copyright 2016 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1046A_COMMON_H
#define __LS1046A_COMMON_H

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP
#define CONFIG_GICV2

#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_func

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT

#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1f000		/* 124 KiB */
#define CONFIG_SPL_STACK		0x10020000
#define CONFIG_SPL_PAD_TO		0x21000		/* 132 KiB */
#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SYS_MONITOR_LEN		0xa0000
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT

#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1d000		/* 116 KiB */
#define CONFIG_SPL_STACK		0x1001f000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SYS_MONITOR_LEN		0xa0000
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4

/* Command line configuration */
#define CONFIG_CMD_ENV

/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif

#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */

/* FMan ucode */
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000

#ifdef CONFIG_SD_BOOT
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x40300000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR		(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x1000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyS0,115200\0"                \
		MTDPARTS_DEFAULT "\0"

#define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
					"earlycon=uart8250,mmio,0x21c0500 " \
					MTDPARTS_DEFAULT
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

#endif /* __LS1046A_COMMON_H */
Commit	Line	Data
dd02936f MH	1	/*
	2	* Copyright 2016 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1046A_COMMON_H
	8	#define __LS1046A_COMMON_H
	9
	10	#define CONFIG_REMAKE_ELF
	11	#define CONFIG_FSL_LAYERSCAPE
dd02936f	12	#define CONFIG_MP
dd02936f MH	13	#define CONFIG_GICV2
	14
	15	#include <asm/arch/config.h>
b52a0507	16	#include <asm/arch/stream_id_lsch2.h>
dd02936f MH	17
	18	/* Link Definitions */
	19	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	20
	21	#define CONFIG_SUPPORT_RAW_INITRD
	22
	23	#define CONFIG_SKIP_LOWLEVEL_INIT
dd02936f MH	24
	25	#define CONFIG_VERY_BIG_RAM
	26	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	27	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	28	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	29	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
	30
	31	#define CPU_RELEASE_ADDR secondary_boot_func
	32
	33	/* Generic Timer Definitions */
	34	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	35
	36	/* Size of malloc() pool */
	37	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	38
	39	/* Serial Port */
	40	#define CONFIG_CONS_INDEX 1
	41	#define CONFIG_SYS_NS16550_SERIAL
	42	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	43	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
dd02936f	44
dd02936f MH	45	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	46
	47	/* SD boot SPL */
	48	#ifdef CONFIG_SD_BOOT
	49	#define CONFIG_SPL_FRAMEWORK
	50	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	51	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	52	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	53	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	54	#define CONFIG_SPL_ENV_SUPPORT
	55	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	56	#define CONFIG_SPL_WATCHDOG_SUPPORT
	57	#define CONFIG_SPL_I2C_SUPPORT
	58	#define CONFIG_SPL_SERIAL_SUPPORT
	59	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	60
	61	#define CONFIG_SPL_MMC_SUPPORT
dd02936f MH	62	#define CONFIG_SPL_TEXT_BASE 0x10000000
	63	#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
	64	#define CONFIG_SPL_STACK 0x10020000
	65	#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
	66	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
	67	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	68	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	69	CONFIG_SPL_BSS_MAX_SIZE)
	70	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	71	#define CONFIG_SYS_MONITOR_LEN 0xa0000
	72	#endif
	73
126fe70d SX	74	/* NAND SPL */
	75	#ifdef CONFIG_NAND_BOOT
	76	#define CONFIG_SPL_PBL_PAD
	77	#define CONFIG_SPL_FRAMEWORK
	78	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	79	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	80	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	81	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	82	#define CONFIG_SPL_ENV_SUPPORT
	83	#define CONFIG_SPL_WATCHDOG_SUPPORT
	84	#define CONFIG_SPL_I2C_SUPPORT
	85	#define CONFIG_SPL_SERIAL_SUPPORT
	86	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	87
	88	#define CONFIG_SPL_NAND_SUPPORT
	89	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	90	#define CONFIG_SPL_TEXT_BASE 0x10000000
	91	#define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */
	92	#define CONFIG_SPL_STACK 0x1001f000
	93	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	94	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	95
	96	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
	97	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	98	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	99	CONFIG_SPL_BSS_MAX_SIZE)
	100	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	101	#define CONFIG_SYS_MONITOR_LEN 0xa0000
	102	#endif
	103
dd02936f MH	104	/* I2C */
	105	#define CONFIG_SYS_I2C
	106	#define CONFIG_SYS_I2C_MXC
	107	#define CONFIG_SYS_I2C_MXC_I2C1
	108	#define CONFIG_SYS_I2C_MXC_I2C2
	109	#define CONFIG_SYS_I2C_MXC_I2C3
	110	#define CONFIG_SYS_I2C_MXC_I2C4
	111
	112	/* Command line configuration */
	113	#define CONFIG_CMD_ENV
	114
	115	/* MMC */
dd02936f MH	116	#ifdef CONFIG_MMC
	117	#define CONFIG_FSL_ESDHC
	118	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
dd02936f MH	119	#endif
dd02936f MH	120
dd02936f MH	121	#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
	122
	123	/* FMan ucode */
	124	#define CONFIG_SYS_DPAA_FMAN
	125	#ifdef CONFIG_SYS_DPAA_FMAN
	126	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
	127
	128	#ifdef CONFIG_SD_BOOT
	129	/*
	130	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
	131	* about 1MB (2048 blocks), Env is stored after the image, and the env size is
	132	* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
	133	*/
	134	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
	135	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
126fe70d	136	#elif defined(CONFIG_QSPI_BOOT)
dd02936f MH	137	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
	138	#define CONFIG_SYS_FMAN_FW_ADDR 0x40300000
	139	#define CONFIG_ENV_SPI_BUS 0
	140	#define CONFIG_ENV_SPI_CS 0
	141	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	142	#define CONFIG_ENV_SPI_MODE 0x03
126fe70d SX	143	#elif defined(CONFIG_NAND_BOOT)
	144	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
	145	#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
	146	#else
	147	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
	148	#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
dd02936f MH	149	#endif
	150	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	151	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	152	#endif
	153
	154	/* Miscellaneous configurable options */
	155	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
dd02936f MH	156
	157	#define CONFIG_HWCONFIG
	158	#define HWCONFIG_BUFFER_SIZE 128
	159
	160	/* Initial environment variables */
	161	#define CONFIG_EXTRA_ENV_SETTINGS \
	162	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	163	"loadaddr=0x80100000\0" \
	164	"ramdisk_addr=0x800000\0" \
	165	"ramdisk_size=0x2000000\0" \
	166	"fdt_high=0xffffffffffffffff\0" \
	167	"initrd_high=0xffffffffffffffff\0" \
	168	"kernel_start=0x1000000\0" \
	169	"kernel_load=0xa0000000\0" \
	170	"kernel_size=0x2800000\0" \
	171	"console=ttyS0,115200\0" \
	172	MTDPARTS_DEFAULT "\0"
	173
	174	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
	175	"earlycon=uart8250,mmio,0x21c0500 " \
	176	MTDPARTS_DEFAULT
	177	/* Monitor Command Prompt */
	178	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	179	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	180	sizeof(CONFIG_SYS_PROMPT) + 16)
	181	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	182	#define CONFIG_SYS_LONGHELP
	183	#define CONFIG_CMDLINE_EDITING 1
	184	#define CONFIG_AUTO_COMPLETE
	185	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	186
	187	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	188
	189	/* Hash command with SHA acceleration supported in hardware */
	190	#ifdef CONFIG_FSL_CAAM
	191	#define CONFIG_CMD_HASH
	192	#define CONFIG_SHA_HW_ACCEL
	193	#endif
	194
	195	#endif /* __LS1046A_COMMON_H */