[thirdparty/u-boot.git] / include / configs / ls1088a_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2017-2018 NXP
 */

#ifndef __LS1088_COMMON_H
#define __LS1088_COMMON_H

/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_BOARDINFO
#define SPL_NO_QIXIS
#define SPL_NO_PCI
#define SPL_NO_ENV
#define SPL_NO_RTC
#define SPL_NO_USB
#define SPL_NO_SATA
#define SPL_NO_QSPI
#define SPL_NO_IFC
#undef CONFIG_DISPLAY_CPUINFO
#endif

#define CONFIG_REMAKE_ELF

#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#include <asm/arch/soc.h>

#define LS1088ARDB_PB_BOARD            0x4A
/* Link Definitions */
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
#else
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#endif

/* Link Definitions */
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
#else
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
#endif
#endif

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	1
/*
 * SMP Definitinos
 */
#define CPU_RELEASE_ADDR		secondary_boot_func

#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)

/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#endif


/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
/* IFC */
#define CONFIG_FSL_IFC
#endif

/*
 * During booting, IFC is mapped at the region of 0x30000000.
 * But this region is limited to 256MB. To accommodate NOR, promjet
 * and FPGA. This region is divided as below:
 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 *
 * To accommodate bigger NOR flash and other devices, we will map IFC
 * chip selects to as below:
 * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
 * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
 * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
 * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
 * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
 *
 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 */

#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000

#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
#endif

#define QIXIS_BASE				get_qixis_addr()
#define QIXIS_BASE_PHYS				0x20000000
#define QIXIS_BASE_PHYS_EARLY			0xC000000


#define CONFIG_SYS_NAND_BASE			0x530000000ULL
#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000


/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000

/* Define phy_reset function to boot the MC based on mcinitcmd.
 * This happens late enough to properly fixup u-boot env MAC addresses.
 */
#define CONFIG_RESET_PHY_R

/*
 * Carve out a DDR region which will not be used by u-boot/Linux
 *
 * It will be used by MC and Debug Server. The MC region must be
 * 512MB aligned, so the min size to hide is 512MB.
 */

#if defined(CONFIG_FSL_MC_ENET)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
#endif
/* Command line configuration */
#define CONFIG_CMD_CACHE

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

/* SATA */
#ifdef CONFIG_SCSI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1		AHCI_BASE_ADDR1

#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
#define CONFIG_SYS_SCSI_MAX_LUN		1
#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
					CONFIG_SYS_SCSI_MAX_LUN)
#endif

/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

/* #define CONFIG_DISPLAY_CPUINFO */

#ifndef SPL_NO_ENV
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyAMA0,38400n8\0"		\
	"mcinitcmd=fsl_mc start mc 0x580a00000"	\
	" 0x580e00000 \0"

#ifndef CONFIG_TFABOOT
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND	"sf probe 0:0;" \
				"sf read 0x80001000 0xd00000 0x100000;"\
				" fsl_mc lazyapply dpl 0x80001000 &&" \
				" sf read $kernel_load $kernel_start" \
				" $kernel_size && bootm $kernel_load"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND	"mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
				" fsl_mc lazyapply dpl 0x80001000 &&" \
				" mmc read $kernel_load $kernel_start" \
				" $kernel_size && bootm $kernel_load"
#else /* NOR BOOT*/
#define CONFIG_BOOTCOMMAND	"fsl_mc lazyapply dpl 0x580d00000 &&" \
				" cp.b $kernel_start $kernel_load" \
				" $kernel_size && bootm $kernel_load"
#endif
#endif /* CONFIG_TFABOOT  */
#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#ifdef CONFIG_SPL
#define CONFIG_SPL_BSS_START_ADDR      0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE                0x00100000
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE            0x16000
#define CONFIG_SPL_STACK               (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"

#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
#define CONFIG_SYS_SPL_MALLOC_START    0x80200000

#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN         (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN         0x100000
#endif /* ifdef CONFIG_NXP_ESBC */

#endif
#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

#endif /* __LS1088_COMMON_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
e84a324b	2	/*
5b595df3	3	* Copyright 2017-2018 NXP
e84a324b AK	4	*/
	5
	6	#ifndef __LS1088_COMMON_H
	7	#define __LS1088_COMMON_H
	8
10e7eaf0 SG	9	/* SPL build */
	10	#ifdef CONFIG_SPL_BUILD
	11	#define SPL_NO_BOARDINFO
	12	#define SPL_NO_QIXIS
	13	#define SPL_NO_PCI
	14	#define SPL_NO_ENV
	15	#define SPL_NO_RTC
	16	#define SPL_NO_USB
	17	#define SPL_NO_SATA
	18	#define SPL_NO_QSPI
	19	#define SPL_NO_IFC
	20	#undef CONFIG_DISPLAY_CPUINFO
	21	#endif
e84a324b AK	22
e84a324b AK	23	#define CONFIG_REMAKE_ELF
e84a324b AK	24
	25	#include <asm/arch/stream_id_lsch3.h>
	26	#include <asm/arch/config.h>
	27	#include <asm/arch/soc.h>
	28
5b595df3	29	#define LS1088ARDB_PB_BOARD 0x4A
e84a324b	30	/* Link Definitions */
143af3c6 PG	31	#ifdef CONFIG_TFABOOT
	32	#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
	33	#else
e84a324b	34	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
143af3c6	35	#endif
e84a324b AK	36
e84a324b AK	37	/* Link Definitions */
143af3c6 PG	38	#ifdef CONFIG_TFABOOT
	39	#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
	40	#else
2eb2dbd4 AK	41	#ifdef CONFIG_QSPI_BOOT
2eb2dbd4 AK	42	#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
2eb2dbd4	43	#endif
143af3c6	44	#endif
e84a324b AK	45
	46	#define CONFIG_SKIP_LOWLEVEL_INIT
	47
e84a324b AK	48	#define CONFIG_VERY_BIG_RAM
	49	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	50	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	51	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	52	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
	53	#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
	54	/*
	55	* SMP Definitinos
	56	*/
	57	#define CPU_RELEASE_ADDR secondary_boot_func
	58
4950eb4a HZ	59	#ifdef CONFIG_PCI
	60	#define CONFIG_CMD_PCI
	61	#endif
	62
e84a324b AK	63	/* Size of malloc() pool */
	64	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
	65
	66	/* I2C */
5dd043a0	67	#ifndef CONFIG_DM_I2C
e84a324b	68	#define CONFIG_SYS_I2C
5dd043a0 CH	69	#endif
5dd043a0 CH	70
e84a324b AK	71
e84a324b AK	72	/* Serial Port */
e84a324b AK	73	#define CONFIG_SYS_NS16550_SERIAL
	74	#define CONFIG_SYS_NS16550_REG_SIZE 1
	75	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
	76
	77	#define CONFIG_BAUDRATE 115200
	78	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	79
10e7eaf0	80	#if !defined(SPL_NO_IFC) \|\| defined(CONFIG_TARGET_LS1088AQDS)
e84a324b AK	81	/* IFC */
e84a324b AK	82	#define CONFIG_FSL_IFC
10e7eaf0	83	#endif
e84a324b AK	84
	85	/*
	86	* During booting, IFC is mapped at the region of 0x30000000.
	87	* But this region is limited to 256MB. To accommodate NOR, promjet
	88	* and FPGA. This region is divided as below:
	89	* 0x30000000 - 0x37ffffff : 128MB : NOR flash
	90	* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
	91	* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
	92	*
	93	* To accommodate bigger NOR flash and other devices, we will map IFC
	94	* chip selects to as below:
	95	* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
	96	* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
	97	* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
	98	* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
	99	* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
	100	*
	101	* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
	102	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	103	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	104	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	105	* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
	106	*/
	107
	108	#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
	109	#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
	110	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	111
	112	#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
	113	#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
	114
	115	#ifndef __ASSEMBLY__
	116	unsigned long long get_qixis_addr(void);
	117	#endif
	118
	119	#define QIXIS_BASE get_qixis_addr()
	120	#define QIXIS_BASE_PHYS 0x20000000
	121	#define QIXIS_BASE_PHYS_EARLY 0xC000000
	122
	123
	124	#define CONFIG_SYS_NAND_BASE 0x530000000ULL
	125	#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
	126
	127
	128	/* MC firmware */
	129	/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
	130	#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
	131	#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
	132	#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
	133	#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
	134	#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
	135	#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
c48deb90 BP	136
	137	/* Define phy_reset function to boot the MC based on mcinitcmd.
	138	* This happens late enough to properly fixup u-boot env MAC addresses.
	139	*/
	140	#define CONFIG_RESET_PHY_R
	141
e84a324b AK	142	/*
	143	* Carve out a DDR region which will not be used by u-boot/Linux
	144	*
	145	* It will be used by MC and Debug Server. The MC region must be
	146	* 512MB aligned, so the min size to hide is 512MB.
	147	*/
	148
	149	#if defined(CONFIG_FSL_MC_ENET)
43ad41e6	150	#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
e84a324b	151	#endif
e84a324b	152	/* Command line configuration */
e84a324b AK	153	#define CONFIG_CMD_CACHE
	154
	155	/* Miscellaneous configurable options */
	156	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
	157
f65425fb AK	158	/* SATA */
f65425fb AK	159	#ifdef CONFIG_SCSI
f65425fb AK	160	#define CONFIG_SCSI_AHCI_PLAT
	161	#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
	162
	163	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	164	#define CONFIG_SYS_SCSI_MAX_LUN 1
	165	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	166	CONFIG_SYS_SCSI_MAX_LUN)
	167	#endif
	168
e84a324b AK	169	/* Physical Memory Map */
	170	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	171
e84a324b AK	172	#define CONFIG_HWCONFIG
	173	#define HWCONFIG_BUFFER_SIZE 128
	174
	175	/* #define CONFIG_DISPLAY_CPUINFO */
	176
10e7eaf0	177	#ifndef SPL_NO_ENV
e84a324b AK	178	/* Allow to overwrite serial and ethaddr */
	179	#define CONFIG_ENV_OVERWRITE
	180
	181	/* Initial environment variables */
	182	#define CONFIG_EXTRA_ENV_SETTINGS \
	183	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	184	"loadaddr=0x80100000\0" \
	185	"kernel_addr=0x100000\0" \
	186	"ramdisk_addr=0x800000\0" \
	187	"ramdisk_size=0x2000000\0" \
	188	"fdt_high=0xa0000000\0" \
	189	"initrd_high=0xffffffffffffffff\0" \
	190	"kernel_start=0x581000000\0" \
	191	"kernel_load=0xa0000000\0" \
	192	"kernel_size=0x2800000\0" \
	193	"console=ttyAMA0,38400n8\0" \
	194	"mcinitcmd=fsl_mc start mc 0x580a00000" \
	195	" 0x580e00000 \0"
	196
143af3c6	197	#ifndef CONFIG_TFABOOT
e84a324b AK	198	#if defined(CONFIG_QSPI_BOOT)
e84a324b AK	199	#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
f4ef476d JG	200	"sf read 0x80001000 0xd00000 0x100000;"\
f4ef476d JG	201	" fsl_mc lazyapply dpl 0x80001000 &&" \
e84a324b AK	202	" sf read $kernel_load $kernel_start" \
e84a324b AK	203	" $kernel_size && bootm $kernel_load"
099f4093	204	#elif defined(CONFIG_SD_BOOT)
f4ef476d JG	205	#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
f4ef476d JG	206	" fsl_mc lazyapply dpl 0x80001000 &&" \
099f4093 AK	207	" mmc read $kernel_load $kernel_start" \
099f4093 AK	208	" $kernel_size && bootm $kernel_load"
e84a324b	209	#else /* NOR BOOT*/
f4ef476d	210	#define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
e84a324b AK	211	" cp.b $kernel_start $kernel_load" \
	212	" $kernel_size && bootm $kernel_load"
	213	#endif
143af3c6	214	#endif /* CONFIG_TFABOOT */
10e7eaf0	215	#endif
e84a324b AK	216
	217	/* Monitor Command Prompt */
	218	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	219	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	220	sizeof(CONFIG_SYS_PROMPT) + 16)
e84a324b	221	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
e84a324b AK	222	#define CONFIG_SYS_MAXARGS 64 /* max command args */
e84a324b AK	223
099f4093 AK	224	#ifdef CONFIG_SPL
	225	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	226	#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
099f4093 AK	227	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	228	#define CONFIG_SPL_MAX_SIZE 0x16000
	229	#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
4b5892c4	230	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
099f4093 AK	231
	232	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
	233	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
1cabeb88	234
5536c3c9	235	#ifdef CONFIG_NXP_ESBC
1cabeb88 SG	236	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	237	/*
	238	* HDR would be appended at end of image and copied to DDR along
	239	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	240	* size increases then increase this size in case of secure boot as
	241	* it uses raw u-boot image instead of fit image.
	242	*/
	243	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	244	#else
	245	#define CONFIG_SYS_MONITOR_LEN 0x100000
5536c3c9	246	#endif /* ifdef CONFIG_NXP_ESBC */
1cabeb88	247
099f4093	248	#endif
e84a324b AK	249	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	250
	251	#endif /* __LS1088_COMMON_H */