[people/ms/u-boot.git] / include / configs / ls2080a_simu.h

/*
 * Copyright (C) 2014 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_SIMU_H
#define __LS2_SIMU_H

#include "ls2080a_common.h"

#ifdef CONFIG_LS2080A
#define CONFIG_IDENT_STRING		" LS2080A-SIMU"
#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2080A-SIMU"
#endif

#ifdef CONFIG_LS2085A
#define CONFIG_IDENT_STRING		" LS2085A-SIMU"
#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-SIMU"
#endif

#define CONFIG_SYS_CLK_FREQ	100000000
#define CONFIG_DDR_CLK_FREQ	133333333

#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
#define CONFIG_SYS_MXC_I2C2_SPEED	40000000

#define CONFIG_DIMM_SLOTS_PER_CTLR		1
#define CONFIG_CHIP_SELECTS_PER_CTRL		4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
#endif

/* SMSC 91C111 ethernet configuration */
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE	(0x2210000)

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)

/*
 * NOR Flash Timing Params
 */
#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
				FTIM0_NOR_TEADC(0x1) | \
				FTIM0_NOR_TEAHC(0x1))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
				FTIM1_NOR_TRAD_NOR(0x1))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
				FTIM2_NOR_TCH(0x0) | \
				FTIM2_NOR_TWP(0x1))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif

#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2


#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3

/*  MMC  */
#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL

/* MC firmware */
#define CONFIG_SYS_LS_MC_FW_IN_NOR
#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL

#define CONFIG_SYS_LS_MC_DPL_IN_NOR
#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL

#define CONFIG_SYS_LS_MC_DPC_IN_NOR
#define CONFIG_SYS_LS_MC_DPC_ADDR	0x5806F8000ULL

#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000

/* Store environment at top of flash */
#define CONFIG_ENV_IS_NOWHERE		1
#define CONFIG_ENV_SIZE			0x1000

#endif /* __LS2_SIMU_H */
Commit	Line	Data
f749db3a YS	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS2_SIMU_H
	8	#define __LS2_SIMU_H
	9
44937214	10	#include "ls2080a_common.h"
f749db3a	11
06b53010	12	#ifdef CONFIG_LS2080A
44937214 PK	13	#define CONFIG_IDENT_STRING " LS2080A-SIMU"
44937214 PK	14	#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU"
06b53010 PK	15	#endif
	16
	17	#ifdef CONFIG_LS2085A
	18	#define CONFIG_IDENT_STRING " LS2085A-SIMU"
	19	#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU"
	20	#endif
bbeeb8be	21
f3f8c564 PK	22	#define CONFIG_SYS_CLK_FREQ 100000000
	23	#define CONFIG_DDR_CLK_FREQ 133333333
	24
	25	#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
	26	#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
	27
	28	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	29	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
44937214	30	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
f3f8c564	31	#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44937214	32	#endif
f3f8c564	33
f749db3a YS	34	/* SMSC 91C111 ethernet configuration */
	35	#define CONFIG_SMC91111
	36	#define CONFIG_SMC91111_BASE (0x2210000)
	37
f3f8c564 PK	38	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	39	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	40
	41	/*
	42	* NOR Flash Timing Params
	43	*/
	44	#define CONFIG_SYS_NOR0_CSPR \
	45	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	46	CSPR_PORT_SIZE_16 \| \
	47	CSPR_MSEL_NOR \| \
	48	CSPR_V)
	49	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	50	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	51	CSPR_PORT_SIZE_16 \| \
	52	CSPR_MSEL_NOR \| \
	53	CSPR_V)
	54	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	55	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) \| \
	56	FTIM0_NOR_TEADC(0x1) \| \
	57	FTIM0_NOR_TEAHC(0x1))
	58	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) \| \
	59	FTIM1_NOR_TRAD_NOR(0x1))
	60	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) \| \
	61	FTIM2_NOR_TCH(0x0) \| \
	62	FTIM2_NOR_TWP(0x1))
	63	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	64	#define CONFIG_SYS_IFC_CCR 0x01000000
	65
	66	#ifndef CONFIG_SYS_NO_FLASH
	67	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	68
	69	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	70	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	71	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	72	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	73
	74	#define CONFIG_SYS_FLASH_EMPTY_INFO
	75	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	76	#endif
	77
	78	#define CONFIG_NAND_FSL_IFC
	79	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	80	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	81
	82
	83	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	84	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	85	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	86	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	87	\| CSPR_V)
	88	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	89
	90	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	91	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	92	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	93	\| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
	94	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	95	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
	96	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	97
	98	#define CONFIG_SYS_NAND_ONFI_DETECTION
	99
	100	/* ONFI NAND Flash mode0 Timing Params */
	101	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
102	FTIM0_NAND_TWP(0x18) \| \
103	FTIM0_NAND_TWCHT(0x07) \| \
104	FTIM0_NAND_TWH(0x0a))
105	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
106	FTIM1_NAND_TWBE(0x39) \| \
107	FTIM1_NAND_TRR(0x0e) \| \
108	FTIM1_NAND_TRP(0x18))
109	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
110	FTIM2_NAND_TREH(0x0a) \| \
111	FTIM2_NAND_TWHRE(0x1e))
112	#define CONFIG_SYS_NAND_FTIM3 0x0
113
114	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
115	#define CONFIG_SYS_MAX_NAND_DEVICE 1
116	#define CONFIG_MTD_NAND_VERIFY_WRITE
117	#define CONFIG_CMD_NAND
118
119	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
120
121	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
122	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
123	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
124	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
125	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
126	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
127	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
128	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
129	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
e211c12e PK	130	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	131	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	132	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	133	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	134	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	135	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	136	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	137	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
	138
b22b8e98 YL	139	/* MMC */
	140	#define CONFIG_MMC
	141	#ifdef CONFIG_MMC
	142	#define CONFIG_CMD_MMC
	143	#define CONFIG_FSL_ESDHC
	144	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
	145	#define CONFIG_GENERIC_MMC
	146	#define CONFIG_CMD_FAT
	147	#define CONFIG_DOS_PARTITION
	148	#endif
	149
f3f8c564 PK	150	/* Debug Server firmware */
	151	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	152	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
	153
	154	/* MC firmware */
	155	#define CONFIG_SYS_LS_MC_FW_IN_NOR
	156	#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
	157
	158	#define CONFIG_SYS_LS_MC_DPL_IN_NOR
	159	#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
	160
125e2bc1 GR	161	#define CONFIG_SYS_LS_MC_DPC_IN_NOR
	162	#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
	163
	164	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
	165
f3f8c564 PK	166	/* Store environment at top of flash */
	167	#define CONFIG_ENV_IS_NOWHERE 1
	168	#define CONFIG_ENV_SIZE 0x1000
	169
f749db3a	170	#endif /* __LS2_SIMU_H */