[people/ms/u-boot.git] / include / configs / ls2080aqds.h

/*
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_QDS_H
#define __LS2_QDS_H

#include "ls2080a_common.h"

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#ifdef CONFIG_FSL_QSPI
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_EARLY_INIT
#define CONFIG_SYS_I2C_IFDR_DIV		0x7e
#endif

#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)

#define CONFIG_DDR_SPD
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS3	0x53
#define SPD_EEPROM_ADDRESS4	0x54
#define SPD_EEPROM_ADDRESS5	0x55
#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR		2
#define CONFIG_CHIP_SELECTS_PER_CTRL		4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
#endif
#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */

/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SCSI
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2			AHCI_BASE_ADDR2

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_PARTITION_UUIDS
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_GPT

/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1a) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
					 CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif

#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH		0x06
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_QSPI		0x0f
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RCW_SRC_NAND		0x107
#define QIXIS_RCW_SRC_QSPI		0x62
#define	QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_CSPR3_EXT	(0x0)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3		0x0

#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		(896 * 1024)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_SPL_PAD_TO		0x20000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3

#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_TEXT_BASE		0x20010000
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x2000
#endif
#endif

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL

#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

/*
 * I2C
 */
#define I2C_MUX_PCA_ADDR		0x77
#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT      0x8

/* SPI */
#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH

#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_EON
#endif

#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE		(1 << 26) /* 64MB */
#define FSL_QSPI_FLASH_NUM		4
#endif
/*
 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 */
#define FSL_QIXIS_BRDCFG9_QSPI		0x1

#endif

/*
 * MMC
 */
#ifdef CONFIG_MMC
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
#endif

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS3231               1
#define CONFIG_SYS_I2C_RTC_ADDR         0x68
#define CONFIG_CMD_DATE

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

#define CONFIG_FSL_MEMAC

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif

/*  MMC  */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#endif

/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581100000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcinitcmd=esbc_validate 0x580c80000;"  \
	"esbc_validate 0x580cc0000;"            \
	"fsl_mc start mc 0x580300000"           \
	" 0x580800000 \0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581100000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcinitcmd=fsl_mc start mc 0x580300000" \
	" 0x580800000 \0"
#endif /* CONFIG_SECURE_BOOT */


#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
#define	CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F

#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf

#define CONFIG_MII		/* MII PHY management */
#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */

#endif

/*
 * USB
 */
#define CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2

#include <asm/fsl_secure_boot.h>

#endif /* __LS2_QDS_H */
Commit	Line	Data
7288c2c2 YS	1	/*
	2	* Copyright 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS2_QDS_H
	8	#define __LS2_QDS_H
	9
44937214	10	#include "ls2080a_common.h"
7288c2c2	11
7288c2c2 YS	12	#ifndef __ASSEMBLY__
	13	unsigned long get_board_sys_clk(void);
	14	unsigned long get_board_ddr_clk(void);
	15	#endif
	16
8c77ef85 YY	17	#ifdef CONFIG_FSL_QSPI
	18	#define CONFIG_SYS_NO_FLASH
	19	#undef CONFIG_CMD_IMLS
	20	#define CONFIG_QIXIS_I2C_ACCESS
	21	#define CONFIG_SYS_I2C_EARLY_INIT
	22	#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
	23	#endif
	24
	25	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
7288c2c2 YS	26	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
	27	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
	28	#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
	29
	30	#define CONFIG_DDR_SPD
	31	#define CONFIG_DDR_ECC
	32	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	33	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	34	#define SPD_EEPROM_ADDRESS1 0x51
	35	#define SPD_EEPROM_ADDRESS2 0x52
	36	#define SPD_EEPROM_ADDRESS3 0x53
	37	#define SPD_EEPROM_ADDRESS4 0x54
	38	#define SPD_EEPROM_ADDRESS5 0x55
	39	#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
	40	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
	41	#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
	42	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	43	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
44937214	44	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
7288c2c2	45	#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44937214	46	#endif
7288c2c2 YS	47	#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
7288c2c2 YS	48
989c5f0a TY	49	/* SATA */
	50	#define CONFIG_LIBATA
	51	#define CONFIG_SCSI_AHCI
	52	#define CONFIG_SCSI_AHCI_PLAT
c649e3c9	53	#define CONFIG_SCSI
989c5f0a TY	54	#define CONFIG_DOS_PARTITION
	55	#define CONFIG_BOARD_LATE_INIT
	56
	57	#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
	58	#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
	59
	60	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	61	#define CONFIG_SYS_SCSI_MAX_LUN 1
	62	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	63	CONFIG_SYS_SCSI_MAX_LUN)
9e0bb4c1 PK	64	#define CONFIG_PARTITION_UUIDS
	65	#define CONFIG_EFI_PARTITION
	66	#define CONFIG_CMD_GPT
989c5f0a	67
7288c2c2 YS	68	/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
	69
	70	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	71	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	72	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(6410241024)
	73
	74	#define CONFIG_SYS_NOR0_CSPR \
	75	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	76	CSPR_PORT_SIZE_16 \| \
	77	CSPR_MSEL_NOR \| \
	78	CSPR_V)
	79	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	80	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	81	CSPR_PORT_SIZE_16 \| \
	82	CSPR_MSEL_NOR \| \
	83	CSPR_V)
	84	#define CONFIG_SYS_NOR1_CSPR \
	85	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) \| \
	86	CSPR_PORT_SIZE_16 \| \
	87	CSPR_MSEL_NOR \| \
	88	CSPR_V)
	89	#define CONFIG_SYS_NOR1_CSPR_EARLY \
	90	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) \| \
	91	CSPR_PORT_SIZE_16 \| \
	92	CSPR_MSEL_NOR \| \
	93	CSPR_V)
	94	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	95	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	96	FTIM0_NOR_TEADC(0x5) \| \
	97	FTIM0_NOR_TEAHC(0x5))
	98	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	99	FTIM1_NOR_TRAD_NOR(0x1a) \|\
	100	FTIM1_NOR_TSEQRAD_NOR(0x13))
	101	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	102	FTIM2_NOR_TCH(0x4) \| \
	103	FTIM2_NOR_TWPH(0x0E) \| \
	104	FTIM2_NOR_TWP(0x1c))
	105	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	106	#define CONFIG_SYS_IFC_CCR 0x01000000
	107
	108	#ifndef CONFIG_SYS_NO_FLASH
	109	#define CONFIG_FLASH_CFI_DRIVER
	110	#define CONFIG_SYS_FLASH_CFI
	111	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	112	#define CONFIG_SYS_FLASH_QUIET_TEST
	113	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	114
	115	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	116	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	117	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	118	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	119
	120	#define CONFIG_SYS_FLASH_EMPTY_INFO
	121	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
	122	CONFIG_SYS_FLASH_BASE + 0x40000000}
	123	#endif
	124
	125	#define CONFIG_NAND_FSL_IFC
	126	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	127	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	128
7288c2c2 YS	129	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	130	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	131	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	132	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	133	\| CSPR_V)
	134	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	135
	136	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	137	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	138	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	139	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	140	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	141	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
	142	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	143
	144	#define CONFIG_SYS_NAND_ONFI_DETECTION
	145
	146	/* ONFI NAND Flash mode0 Timing Params */
	147	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	148	FTIM0_NAND_TWP(0x18) \| \
	149	FTIM0_NAND_TWCHT(0x07) \| \
	150	FTIM0_NAND_TWH(0x0a))
	151	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	152	FTIM1_NAND_TWBE(0x39) \| \
	153	FTIM1_NAND_TRR(0x0e) \| \
	154	FTIM1_NAND_TRP(0x18))
	155	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	156	FTIM2_NAND_TREH(0x0a) \| \
	157	FTIM2_NAND_TWHRE(0x1e))
	158	#define CONFIG_SYS_NAND_FTIM3 0x0
	159
	160	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	161	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	162	#define CONFIG_MTD_NAND_VERIFY_WRITE
	163	#define CONFIG_CMD_NAND
	164
	165	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	166
	167	#define CONFIG_FSL_QIXIS /* use common QIXIS code */
	168	#define QIXIS_LBMAP_SWITCH 0x06
	169	#define QIXIS_LBMAP_MASK 0x0f
	170	#define QIXIS_LBMAP_SHIFT 0
	171	#define QIXIS_LBMAP_DFLTBANK 0x00
	172	#define QIXIS_LBMAP_ALTBANK 0x04
b2d5ac59	173	#define QIXIS_LBMAP_NAND 0x09
a646f669	174	#define QIXIS_LBMAP_QSPI 0x0f
7288c2c2 YS	175	#define QIXIS_RST_CTL_RESET 0x31
	176	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	177	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	178	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
b2d5ac59	179	#define QIXIS_RCW_SRC_NAND 0x107
a646f669	180	#define QIXIS_RCW_SRC_QSPI 0x62
7288c2c2 YS	181	#define QIXIS_RST_FORCE_MEM 0x01
	182
	183	#define CONFIG_SYS_CSPR3_EXT (0x0)
	184	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	185	\| CSPR_PORT_SIZE_8 \
	186	\| CSPR_MSEL_GPCM \
	187	\| CSPR_V)
	188	#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	189	\| CSPR_PORT_SIZE_8 \
	190	\| CSPR_MSEL_GPCM \
	191	\| CSPR_V)
	192
	193	#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
	194	#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
	195	/* QIXIS Timing parameters for IFC CS3 */
	196	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	197	FTIM0_GPCM_TEADC(0x0e) \| \
	198	FTIM0_GPCM_TEAHC(0x0e))
	199	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	200	FTIM1_GPCM_TRAD(0x3f))
	201	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	202	FTIM2_GPCM_TCH(0xf) \| \
	203	FTIM2_GPCM_TWP(0x3E))
	204	#define CONFIG_SYS_CS3_FTIM3 0x0
	205
b2d5ac59 SW	206	#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
	207	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	208	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
	209	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
	210	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	211	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	212	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	213	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	214	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	215	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	216	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
	217	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
	218	#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
	219	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
	220	#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
	221	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	222	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	223	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	224	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	225	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	226	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	227	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	228	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	229	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	230	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	231	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	232	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	233	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	234
	235	#define CONFIG_ENV_IS_IN_NAND
	236	#define CONFIG_ENV_OFFSET (896 * 1024)
	237	#define CONFIG_ENV_SECT_SIZE 0x20000
	238	#define CONFIG_ENV_SIZE 0x2000
	239	#define CONFIG_SPL_PAD_TO 0x20000
	240	#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
74cac00c	241	#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
b2d5ac59	242	#else
7288c2c2 YS	243	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	244	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	245	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	246	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	247	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	248	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	249	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	250	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	251	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	252	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	253	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
	254	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
	255	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
	256	#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
	257	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	258	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	259	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	260	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	261	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	262	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	263	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	264	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	265	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	266	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	267	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	268	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	269	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	270
a646f669 YY	271	#if defined(CONFIG_QSPI_BOOT)
	272	#define CONFIG_SYS_TEXT_BASE 0x20010000
	273	#define CONFIG_ENV_IS_IN_SPI_FLASH
	274	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	275	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	276	#define CONFIG_ENV_SECT_SIZE 0x10000
	277	#else
b2d5ac59 SW	278	#define CONFIG_ENV_IS_IN_FLASH
	279	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
	280	#define CONFIG_ENV_SECT_SIZE 0x20000
	281	#define CONFIG_ENV_SIZE 0x2000
	282	#endif
a646f669	283	#endif
b2d5ac59	284
7288c2c2 YS	285	/* Debug Server firmware */
	286	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	287	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
	288
7288c2c2 YS	289	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
	290
	291	/*
	292	* I2C
	293	*/
	294	#define I2C_MUX_PCA_ADDR 0x77
	295	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
	296
	297	/* I2C bus multiplexer */
	298	#define I2C_MUX_CH_DEFAULT 0x8
	299
b7774b05	300	/* SPI */
b718d371	301	#if defined(CONFIG_FSL_QSPI) \|\| defined(CONFIG_FSL_DSPI)
b7774b05	302	#define CONFIG_SPI_FLASH
b718d371 YY	303
	304	#ifdef CONFIG_FSL_DSPI
	305	#define CONFIG_SPI_FLASH_STMICRO
	306	#define CONFIG_SPI_FLASH_SST
	307	#define CONFIG_SPI_FLASH_EON
	308	#endif
	309
	310	#ifdef CONFIG_FSL_QSPI
	311	#define CONFIG_SPI_FLASH_SPANSION
	312	#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */
	313	#define FSL_QSPI_FLASH_NUM 4
	314	#endif
453418f2 YY	315	/*
	316	* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
	317	* If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
	318	* If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
	319	*/
	320	#define FSL_QIXIS_BRDCFG9_QSPI 0x1
b718d371	321
b7774b05 HW	322	#endif
b7774b05 HW	323
8b06460e YL	324	/*
	325	* MMC
	326	*/
	327	#ifdef CONFIG_MMC
	328	#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
	329	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
	330	#endif
	331
7288c2c2 YS	332	/*
	333	* RTC configuration
	334	*/
	335	#define RTC
	336	#define CONFIG_RTC_DS3231 1
	337	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
6581440c	338	#define CONFIG_CMD_DATE
7288c2c2 YS	339
	340	/* EEPROM */
	341	#define CONFIG_ID_EEPROM
	342	#define CONFIG_CMD_EEPROM
	343	#define CONFIG_SYS_I2C_EEPROM_NXID
	344	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	345	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	346	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	347	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	348	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	349
7288c2c2	350	#define CONFIG_FSL_MEMAC
7288c2c2 YS	351
7288c2c2 YS	352	#ifdef CONFIG_PCI
7288c2c2 YS	353	#define CONFIG_PCI_SCAN_SHOW
7288c2c2 YS	354	#define CONFIG_CMD_PCI
7288c2c2 YS	355	#endif
7288c2c2 YS	356
8b06460e	357	/* MMC */
8b06460e	358	#ifdef CONFIG_MMC
8b06460e YL	359	#define CONFIG_FSL_ESDHC
	360	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
	361	#define CONFIG_GENERIC_MMC
8b06460e YL	362	#define CONFIG_DOS_PARTITION
8b06460e YL	363	#endif
7288c2c2 YS	364
	365	/* Initial environment variables */
	366	#undef CONFIG_EXTRA_ENV_SETTINGS
9ed44787	367	#ifdef CONFIG_SECURE_BOOT
7288c2c2 YS	368	#define CONFIG_EXTRA_ENV_SETTINGS \
	369	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	370	"loadaddr=0x80100000\0" \
	371	"kernel_addr=0x100000\0" \
	372	"ramdisk_addr=0x800000\0" \
	373	"ramdisk_size=0x2000000\0" \
	374	"fdt_high=0xa0000000\0" \
	375	"initrd_high=0xffffffffffffffff\0" \
	376	"kernel_start=0x581100000\0" \
	377	"kernel_load=0xa0000000\0" \
16ed8560	378	"kernel_size=0x2800000\0" \
9ed44787 UA	379	"mcinitcmd=esbc_validate 0x580c80000;" \
	380	"esbc_validate 0x580cc0000;" \
	381	"fsl_mc start mc 0x580300000" \
16ed8560	382	" 0x580800000 \0"
9ed44787 UA	383	#else
	384	#define CONFIG_EXTRA_ENV_SETTINGS \
	385	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	386	"loadaddr=0x80100000\0" \
	387	"kernel_addr=0x100000\0" \
	388	"ramdisk_addr=0x800000\0" \
	389	"ramdisk_size=0x2000000\0" \
	390	"fdt_high=0xa0000000\0" \
	391	"initrd_high=0xffffffffffffffff\0" \
	392	"kernel_start=0x581100000\0" \
	393	"kernel_load=0xa0000000\0" \
	394	"kernel_size=0x2800000\0" \
	395	"mcinitcmd=fsl_mc start mc 0x580300000" \
	396	" 0x580800000 \0"
	397	#endif /* CONFIG_SECURE_BOOT */
	398
7288c2c2	399
e60476a0 PK	400	#ifdef CONFIG_FSL_MC_ENET
	401	#define CONFIG_FSL_MEMAC
	402	#define CONFIG_PHYLIB
	403	#define CONFIG_PHYLIB_10G
e60476a0 PK	404	#define CONFIG_PHY_VITESSE
	405	#define CONFIG_PHY_REALTEK
	406	#define CONFIG_PHY_TERANETICS
	407	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	408	#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
	409	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	410	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	411
cf7ee6c4 PK	412	#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
	413	#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
	414	#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
	415	#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
	416	#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
	417	#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
	418	#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
	419	#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
	420	#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
	421	#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
	422	#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
	423	#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
	424	#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
	425	#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
	426	#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
	427	#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
	428
e60476a0	429	#define CONFIG_MII /* MII PHY management */
7ad9cc96	430	#define CONFIG_ETHPRIME "DPMAC1@xgmii"
e60476a0 PK	431	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
	432
	433	#endif
	434
94e8cd80 NB	435	/*
	436	* USB
	437	*/
	438	#define CONFIG_HAS_FSL_XHCI_USB
94e8cd80	439	#define CONFIG_USB_XHCI_FSL
94e8cd80 NB	440	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
94e8cd80 NB	441	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
94e8cd80	442
fcfdb6d5 SJ	443	#include <asm/fsl_secure_boot.h>
fcfdb6d5 SJ	444
7288c2c2	445	#endif /* __LS2_QDS_H */