[thirdparty/u-boot.git] / include / configs / ls2080aqds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2017, 2019-2020 NXP
 * Copyright 2015 Freescale Semiconductor
 */

#ifndef __LS2_QDS_H
#define __LS2_QDS_H

#include "ls2080a_common.h"

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
#define CONFIG_SYS_I2C_IFDR_DIV		0x7e
#endif

#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)

#define CONFIG_DDR_SPD
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS3	0x53
#define SPD_EEPROM_ADDRESS4	0x54
#define SPD_EEPROM_ADDRESS5	0x55
#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR		2
#define CONFIG_CHIP_SELECTS_PER_CTRL		4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
#endif

/* SATA */
#define CONFIG_SCSI_AHCI_PLAT

#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2			AHCI_BASE_ADDR2

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)

#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_MMC_ENV_DEV		0
#endif

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1a) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
					 CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif

#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH		0x06
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_QSPI		0x0f
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RCW_SRC_NAND		0x107
#define QIXIS_RCW_SRC_SD		0x40
#define QIXIS_RCW_SRC_QSPI		0x62
#define	QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_CSPR3_EXT	(0x0)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3		0x0

#if defined(CONFIG_SPL)
#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SPL_PAD_TO		0x20000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV		0
#endif
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL

#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

/*
 * I2C
 */
#define I2C_MUX_PCA_ADDR		0x77
#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT      0x8

/* SPI */
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_EON
#endif

#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#endif
/*
 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 */
#define FSL_QIXIS_BRDCFG9_QSPI		0x1

/*
 * MMC
 */
#ifdef CONFIG_MMC
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
#endif

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS3231               1
#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#define CONFIG_SYS_I2C_RTC_ADDR         0x68
#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

#define CONFIG_FSL_MEMAC

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

/*  MMC  */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif

/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcmemsize=0x40000000\0"		\
	"mcinitcmd=esbc_validate 0x580640000;"  \
	"esbc_validate 0x580680000;"            \
	"fsl_mc start mc 0x580a00000"           \
	" 0x580e00000 \0"
#else
#ifdef CONFIG_TFABOOT
#define SD_MC_INIT_CMD				\
	"mmcinfo;mmc read 0x80a00000 0x5000 0x1200;"  \
	"mmc read 0x80e00000 0x7000 0x800;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"
#define IFC_MC_INIT_CMD				\
	"fsl_mc start mc 0x580a00000" \
	" 0x580e00000 \0"
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
	"loadaddr=0x80100000\0"                 \
	"loadaddr_sd=0x90100000\0"                 \
	"kernel_addr=0x581000000\0"		          \
	"kernel_addr_sd=0x8000\0"                \
	"ramdisk_addr=0x800000\0"               \
	"ramdisk_size=0x2000000\0"              \
	"fdt_high=0xa0000000\0"                 \
	"initrd_high=0xffffffffffffffff\0"      \
	"kernel_start=0x581000000\0"            \
	"kernel_start_sd=0x8000\0"              \
	"kernel_load=0xa0000000\0"              \
	"kernel_size=0x2800000\0"               \
	"kernel_size_sd=0x14000\0"               \
	"load_addr=0xa0000000\0"		            \
	"kernelheader_addr=0x580600000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernelheader_size=0x40000\0"		\
	"BOARD=ls2088aqds\0" \
	"mcmemsize=0x70000000 \0" \
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	IFC_MC_INIT_CMD				\
	BOOTENV					\
	"boot_scripts=ls2088aqds_boot.scr\0"	\
	"boot_script_hdr=hdr_ls2088aqds_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} "	\
			"${scriptaddr} ${prefix}${script}; "	\
		"env exists secureboot && load ${devtype} "	\
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"			\
	"nor_bootcmd=echo Trying load from nor..;"		\
		"cp.b $kernel_addr $load_addr "			\
		"$kernel_size ; env exists secureboot && "	\
		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		"bootm $load_addr#$BOARD\0"	\
	"sd_bootcmd=echo Trying load from SD ..;" \
	"mmcinfo; mmc read $load_addr "		\
	"$kernel_addr_sd $kernel_size_sd && "	\
	"bootm $load_addr#$BOARD\0"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
	"loadaddr=0x90100000\0"                 \
	"kernel_addr=0x800\0"                \
	"ramdisk_addr=0x800000\0"               \
	"ramdisk_size=0x2000000\0"              \
	"fdt_high=0xa0000000\0"                 \
	"initrd_high=0xffffffffffffffff\0"      \
	"kernel_start=0x8000\0"              \
	"kernel_load=0xa0000000\0"              \
	"kernel_size=0x14000\0"               \
	"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
	"mmc read 0x80100000 0x7000 0x800;" \
	"fsl_mc start mc 0x80000000 0x80100000\0"       \
	"mcmemsize=0x70000000 \0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcmemsize=0x40000000\0"		\
	"mcinitcmd=fsl_mc start mc 0x580a00000" \
	" 0x580e00000 \0"
#endif /* CONFIG_TFABOOT */
#endif /* CONFIG_NXP_ESBC */

#ifdef CONFIG_TFABOOT
#define BOOT_TARGET_DEVICES(func) \
	func(USB, usb, 0) \
	func(MMC, mmc, 0) \
	func(SCSI, scsi, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

#define SD_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
			"&& esbc_validate $load_addr; "			\
			"env exists mcinitcmd && run mcinitcmd "	\
			"&& mmc read 0x80d00000 0x6800 0x800 "		\
			"&& fsl_mc lazyapply dpl 0x80d00000; "		\
			"run distro_bootcmd;run sd_bootcmd; "		\
			"env exists secureboot && esbc_halt;"

#define IFC_NOR_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
			"&& fsl_mc lazyapply dpl 0x580d00000;"		\
			"run distro_bootcmd;run nor_bootcmd; "		\
			"env exists secureboot && esbc_halt;"
#endif

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F

#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf

#define CONFIG_ETHPRIME		"DPMAC1@xgmii"

#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS2_QDS_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
7288c2c2	2	/*
8526a58a	3	* Copyright 2017, 2019-2020 NXP
7288c2c2	4	* Copyright 2015 Freescale Semiconductor
7288c2c2 YS	5	*/
	6
	7	#ifndef __LS2_QDS_H
	8	#define __LS2_QDS_H
	9
44937214	10	#include "ls2080a_common.h"
7288c2c2	11
7288c2c2 YS	12	#ifndef __ASSEMBLY__
	13	unsigned long get_board_sys_clk(void);
	14	unsigned long get_board_ddr_clk(void);
	15	#endif
	16
8c77ef85	17	#ifdef CONFIG_FSL_QSPI
8c77ef85	18	#define CONFIG_QIXIS_I2C_ACCESS
885ae051	19	#ifndef CONFIG_DM_I2C
8c77ef85	20	#define CONFIG_SYS_I2C_EARLY_INIT
885ae051	21	#endif
8c77ef85 YY	22	#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
	23	#endif
	24
	25	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
7288c2c2 YS	26	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
	27	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
	28	#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
	29
	30	#define CONFIG_DDR_SPD
	31	#define CONFIG_DDR_ECC
	32	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	33	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	34	#define SPD_EEPROM_ADDRESS1 0x51
	35	#define SPD_EEPROM_ADDRESS2 0x52
	36	#define SPD_EEPROM_ADDRESS3 0x53
	37	#define SPD_EEPROM_ADDRESS4 0x54
	38	#define SPD_EEPROM_ADDRESS5 0x55
	39	#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
	40	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
	41	#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
	42	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	43	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
44937214	44	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
7288c2c2	45	#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44937214	46	#endif
7288c2c2	47
989c5f0a	48	/* SATA */
989c5f0a	49	#define CONFIG_SCSI_AHCI_PLAT
989c5f0a TY	50
	51	#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
	52	#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
	53
	54	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	55	#define CONFIG_SYS_SCSI_MAX_LUN 1
	56	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	57	CONFIG_SYS_SCSI_MAX_LUN)
	58
1908201c RB	59	#ifdef CONFIG_TFABOOT
1908201c RB	60	#define CONFIG_SYS_MMC_ENV_DEV 0
1908201c RB	61	#endif
1908201c RB	62
7288c2c2 YS	63	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	64	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	65	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(6410241024)
	66
	67	#define CONFIG_SYS_NOR0_CSPR \
	68	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	69	CSPR_PORT_SIZE_16 \| \
	70	CSPR_MSEL_NOR \| \
	71	CSPR_V)
	72	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	73	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	74	CSPR_PORT_SIZE_16 \| \
	75	CSPR_MSEL_NOR \| \
	76	CSPR_V)
	77	#define CONFIG_SYS_NOR1_CSPR \
	78	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) \| \
	79	CSPR_PORT_SIZE_16 \| \
	80	CSPR_MSEL_NOR \| \
	81	CSPR_V)
	82	#define CONFIG_SYS_NOR1_CSPR_EARLY \
	83	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) \| \
	84	CSPR_PORT_SIZE_16 \| \
	85	CSPR_MSEL_NOR \| \
	86	CSPR_V)
	87	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	88	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	89	FTIM0_NOR_TEADC(0x5) \| \
	90	FTIM0_NOR_TEAHC(0x5))
	91	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	92	FTIM1_NOR_TRAD_NOR(0x1a) \|\
	93	FTIM1_NOR_TSEQRAD_NOR(0x13))
	94	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	95	FTIM2_NOR_TCH(0x4) \| \
	96	FTIM2_NOR_TWPH(0x0E) \| \
	97	FTIM2_NOR_TWP(0x1c))
	98	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	99	#define CONFIG_SYS_IFC_CCR 0x01000000
	100
e856bdcf	101	#ifdef CONFIG_MTD_NOR_FLASH
7288c2c2 YS	102	#define CONFIG_SYS_FLASH_QUIET_TEST
	103	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	104
	105	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	106	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	107	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	108	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	109
	110	#define CONFIG_SYS_FLASH_EMPTY_INFO
	111	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
	112	CONFIG_SYS_FLASH_BASE + 0x40000000}
	113	#endif
	114
	115	#define CONFIG_NAND_FSL_IFC
	116	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	117	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	118
7288c2c2 YS	119	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	120	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	121	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	122	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	123	\| CSPR_V)
	124	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	125
	126	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	127	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	128	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	129	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	130	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	131	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
	132	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	133
	134	#define CONFIG_SYS_NAND_ONFI_DETECTION
	135
	136	/* ONFI NAND Flash mode0 Timing Params */
	137	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	138	FTIM0_NAND_TWP(0x18) \| \
	139	FTIM0_NAND_TWCHT(0x07) \| \
	140	FTIM0_NAND_TWH(0x0a))
	141	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	142	FTIM1_NAND_TWBE(0x39) \| \
	143	FTIM1_NAND_TRR(0x0e) \| \
	144	FTIM1_NAND_TRP(0x18))
	145	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	146	FTIM2_NAND_TREH(0x0a) \| \
	147	FTIM2_NAND_TWHRE(0x1e))
	148	#define CONFIG_SYS_NAND_FTIM3 0x0
	149
	150	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	151	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	152	#define CONFIG_MTD_NAND_VERIFY_WRITE
7288c2c2 YS	153
	154	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	155
	156	#define CONFIG_FSL_QIXIS /* use common QIXIS code */
	157	#define QIXIS_LBMAP_SWITCH 0x06
	158	#define QIXIS_LBMAP_MASK 0x0f
	159	#define QIXIS_LBMAP_SHIFT 0
	160	#define QIXIS_LBMAP_DFLTBANK 0x00
	161	#define QIXIS_LBMAP_ALTBANK 0x04
b2d5ac59	162	#define QIXIS_LBMAP_NAND 0x09
1f55a938	163	#define QIXIS_LBMAP_SD 0x00
a646f669	164	#define QIXIS_LBMAP_QSPI 0x0f
7288c2c2 YS	165	#define QIXIS_RST_CTL_RESET 0x31
	166	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	167	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	168	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
b2d5ac59	169	#define QIXIS_RCW_SRC_NAND 0x107
1f55a938	170	#define QIXIS_RCW_SRC_SD 0x40
a646f669	171	#define QIXIS_RCW_SRC_QSPI 0x62
7288c2c2 YS	172	#define QIXIS_RST_FORCE_MEM 0x01
	173
	174	#define CONFIG_SYS_CSPR3_EXT (0x0)
	175	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	176	\| CSPR_PORT_SIZE_8 \
	177	\| CSPR_MSEL_GPCM \
	178	\| CSPR_V)
	179	#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	180	\| CSPR_PORT_SIZE_8 \
	181	\| CSPR_MSEL_GPCM \
	182	\| CSPR_V)
	183
	184	#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
	185	#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
	186	/* QIXIS Timing parameters for IFC CS3 */
	187	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	188	FTIM0_GPCM_TEADC(0x0e) \| \
	189	FTIM0_GPCM_TEAHC(0x0e))
	190	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	191	FTIM1_GPCM_TRAD(0x3f))
	192	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	193	FTIM2_GPCM_TCH(0xf) \| \
	194	FTIM2_GPCM_TWP(0x3E))
	195	#define CONFIG_SYS_CS3_FTIM3 0x0
	196
faed6bde SK	197	#if defined(CONFIG_SPL)
faed6bde SK	198	#if defined(CONFIG_NAND_BOOT)
b2d5ac59 SW	199	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	200	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
	201	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
	202	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	203	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	204	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	205	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	206	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	207	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	208	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
	209	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
	210	#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
	211	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
	212	#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
	213	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	214	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	215	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	216	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	217	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	218	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	219	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	220	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	221	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	222	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	223	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	224	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	225	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	226
b2d5ac59 SW	227	#define CONFIG_SPL_PAD_TO 0x20000
b2d5ac59 SW	228	#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
74cac00c	229	#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
1f55a938	230	#elif defined(CONFIG_SD_BOOT)
1f55a938	231	#define CONFIG_SYS_MMC_ENV_DEV 0
faed6bde	232	#endif
b2d5ac59	233	#else
7288c2c2 YS	234	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	235	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	236	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	237	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	238	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	239	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	240	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	241	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	242	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	243	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	244	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
	245	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
	246	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
	247	#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
	248	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	249	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	250	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	251	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	252	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	253	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	254	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	255	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	256	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	257	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	258	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	259	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	260	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
a646f669	261	#endif
b2d5ac59	262
7288c2c2 YS	263	/* Debug Server firmware */
	264	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	265	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
	266
7288c2c2 YS	267	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
	268
	269	/*
	270	* I2C
	271	*/
	272	#define I2C_MUX_PCA_ADDR 0x77
	273	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
	274
	275	/* I2C bus multiplexer */
	276	#define I2C_MUX_CH_DEFAULT 0x8
	277
b7774b05	278	/* SPI */
b718d371 YY	279	#ifdef CONFIG_FSL_DSPI
	280	#define CONFIG_SPI_FLASH_STMICRO
	281	#define CONFIG_SPI_FLASH_SST
	282	#define CONFIG_SPI_FLASH_EON
	283	#endif
	284
	285	#ifdef CONFIG_FSL_QSPI
	286	#define CONFIG_SPI_FLASH_SPANSION
b718d371	287	#endif
453418f2 YY	288	/*
	289	* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
	290	* If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
	291	* If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
	292	*/
	293	#define FSL_QIXIS_BRDCFG9_QSPI 0x1
b718d371	294
8b06460e YL	295	/*
	296	* MMC
	297	*/
	298	#ifdef CONFIG_MMC
	299	#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
	300	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
	301	#endif
	302
7288c2c2 YS	303	/*
	304	* RTC configuration
	305	*/
	306	#define RTC
	307	#define CONFIG_RTC_DS3231 1
885ae051	308	#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
7288c2c2	309	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
db07c447	310	#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
7288c2c2 YS	311
	312	/* EEPROM */
	313	#define CONFIG_ID_EEPROM
7288c2c2 YS	314	#define CONFIG_SYS_I2C_EEPROM_NXID
	315	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	316	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	317	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	318	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	319	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	320
7288c2c2	321	#define CONFIG_FSL_MEMAC
7288c2c2 YS	322
7288c2c2 YS	323	#ifdef CONFIG_PCI
7288c2c2	324	#define CONFIG_PCI_SCAN_SHOW
7288c2c2 YS	325	#endif
7288c2c2 YS	326
8b06460e	327	/* MMC */
8b06460e	328	#ifdef CONFIG_MMC
8b06460e	329	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
8b06460e	330	#endif
7288c2c2 YS	331
	332	/* Initial environment variables */
	333	#undef CONFIG_EXTRA_ENV_SETTINGS
5536c3c9	334	#ifdef CONFIG_NXP_ESBC
7288c2c2 YS	335	#define CONFIG_EXTRA_ENV_SETTINGS \
	336	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	337	"loadaddr=0x80100000\0" \
	338	"kernel_addr=0x100000\0" \
	339	"ramdisk_addr=0x800000\0" \
	340	"ramdisk_size=0x2000000\0" \
	341	"fdt_high=0xa0000000\0" \
	342	"initrd_high=0xffffffffffffffff\0" \
7676074a	343	"kernel_start=0x581000000\0" \
7288c2c2	344	"kernel_load=0xa0000000\0" \
16ed8560	345	"kernel_size=0x2800000\0" \
6d7b9e78	346	"mcmemsize=0x40000000\0" \
8526a58a PS	347	"mcinitcmd=esbc_validate 0x580640000;" \
8526a58a PS	348	"esbc_validate 0x580680000;" \
7676074a UA	349	"fsl_mc start mc 0x580a00000" \
7676074a UA	350	" 0x580e00000 \0"
1908201c RB	351	#else
	352	#ifdef CONFIG_TFABOOT
	353	#define SD_MC_INIT_CMD \
c3d141e0 WK	354	"mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
	355	"mmc read 0x80e00000 0x7000 0x800;" \
	356	"fsl_mc start mc 0x80a00000 0x80e00000\0"
1908201c RB	357	#define IFC_MC_INIT_CMD \
	358	"fsl_mc start mc 0x580a00000" \
	359	" 0x580e00000 \0"
	360	#define CONFIG_EXTRA_ENV_SETTINGS \
	361	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	362	"loadaddr=0x80100000\0" \
	363	"loadaddr_sd=0x90100000\0" \
d7a4ddd3 WK	364	"kernel_addr=0x581000000\0" \
d7a4ddd3 WK	365	"kernel_addr_sd=0x8000\0" \
1908201c RB	366	"ramdisk_addr=0x800000\0" \
	367	"ramdisk_size=0x2000000\0" \
	368	"fdt_high=0xa0000000\0" \
	369	"initrd_high=0xffffffffffffffff\0" \
	370	"kernel_start=0x581000000\0" \
	371	"kernel_start_sd=0x8000\0" \
	372	"kernel_load=0xa0000000\0" \
	373	"kernel_size=0x2800000\0" \
	374	"kernel_size_sd=0x14000\0" \
d7a4ddd3	375	"load_addr=0xa0000000\0" \
8526a58a	376	"kernelheader_addr=0x580600000\0" \
d7a4ddd3 WK	377	"kernelheader_addr_r=0x80200000\0" \
	378	"kernelheader_size=0x40000\0" \
	379	"BOARD=ls2088aqds\0" \
	380	"mcmemsize=0x70000000 \0" \
1a9ce6e0 BL	381	"scriptaddr=0x80000000\0" \
1a9ce6e0 BL	382	"scripthdraddr=0x80080000\0" \
d7a4ddd3	383	IFC_MC_INIT_CMD \
1a9ce6e0 BL	384	BOOTENV \
	385	"boot_scripts=ls2088aqds_boot.scr\0" \
	386	"boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
	387	"scan_dev_for_boot_part=" \
	388	"part list ${devtype} ${devnum} devplist; " \
	389	"env exists devplist \|\| setenv devplist 1; " \
	390	"for distro_bootpart in ${devplist}; do " \
	391	"if fstype ${devtype} " \
	392	"${devnum}:${distro_bootpart} " \
	393	"bootfstype; then " \
	394	"run scan_dev_for_boot; " \
	395	"fi; " \
	396	"done\0" \
	397	"boot_a_script=" \
	398	"load ${devtype} ${devnum}:${distro_bootpart} " \
	399	"${scriptaddr} ${prefix}${script}; " \
	400	"env exists secureboot && load ${devtype} " \
	401	"${devnum}:${distro_bootpart} " \
	402	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	403	"&& esbc_validate ${scripthdraddr};" \
	404	"source ${scriptaddr}\0" \
d7a4ddd3 WK	405	"nor_bootcmd=echo Trying load from nor..;" \
	406	"cp.b $kernel_addr $load_addr " \
	407	"$kernel_size ; env exists secureboot && " \
	408	"cp.b $kernelheader_addr $kernelheader_addr_r " \
	409	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
	410	"bootm $load_addr#$BOARD\0" \
	411	"sd_bootcmd=echo Trying load from SD ..;" \
	412	"mmcinfo; mmc read $load_addr " \
	413	"$kernel_addr_sd $kernel_size_sd && " \
	414	"bootm $load_addr#$BOARD\0"
1f55a938 SK	415	#elif defined(CONFIG_SD_BOOT)
	416	#define CONFIG_EXTRA_ENV_SETTINGS \
	417	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	418	"loadaddr=0x90100000\0" \
	419	"kernel_addr=0x800\0" \
	420	"ramdisk_addr=0x800000\0" \
	421	"ramdisk_size=0x2000000\0" \
	422	"fdt_high=0xa0000000\0" \
	423	"initrd_high=0xffffffffffffffff\0" \
	424	"kernel_start=0x8000\0" \
	425	"kernel_load=0xa0000000\0" \
	426	"kernel_size=0x14000\0" \
	427	"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
	428	"mmc read 0x80100000 0x7000 0x800;" \
	429	"fsl_mc start mc 0x80000000 0x80100000\0" \
	430	"mcmemsize=0x70000000 \0"
9ed44787 UA	431	#else
	432	#define CONFIG_EXTRA_ENV_SETTINGS \
	433	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	434	"loadaddr=0x80100000\0" \
	435	"kernel_addr=0x100000\0" \
	436	"ramdisk_addr=0x800000\0" \
	437	"ramdisk_size=0x2000000\0" \
	438	"fdt_high=0xa0000000\0" \
	439	"initrd_high=0xffffffffffffffff\0" \
f5bf23d8	440	"kernel_start=0x581000000\0" \
9ed44787 UA	441	"kernel_load=0xa0000000\0" \
9ed44787 UA	442	"kernel_size=0x2800000\0" \
6d7b9e78	443	"mcmemsize=0x40000000\0" \
f5bf23d8 SK	444	"mcinitcmd=fsl_mc start mc 0x580a00000" \
f5bf23d8 SK	445	" 0x580e00000 \0"
1908201c	446	#endif /* CONFIG_TFABOOT */
5536c3c9	447	#endif /* CONFIG_NXP_ESBC */
9ed44787	448
d7a4ddd3	449	#ifdef CONFIG_TFABOOT
1a9ce6e0 BL	450	#define BOOT_TARGET_DEVICES(func) \
	451	func(USB, usb, 0) \
	452	func(MMC, mmc, 0) \
	453	func(SCSI, scsi, 0) \
	454	func(DHCP, dhcp, na)
	455	#include <config_distro_bootcmd.h>
	456
d7a4ddd3 WK	457	#define SD_BOOTCOMMAND \
d7a4ddd3 WK	458	"env exists mcinitcmd && env exists secureboot "\
8526a58a	459	"&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
d7a4ddd3 WK	460	"&& esbc_validate $load_addr; " \
d7a4ddd3 WK	461	"env exists mcinitcmd && run mcinitcmd " \
c3d141e0 WK	462	"&& mmc read 0x80d00000 0x6800 0x800 " \
c3d141e0 WK	463	"&& fsl_mc lazyapply dpl 0x80d00000; " \
1a9ce6e0	464	"run distro_bootcmd;run sd_bootcmd; " \
d7a4ddd3 WK	465	"env exists secureboot && esbc_halt;"
	466
	467	#define IFC_NOR_BOOTCOMMAND \
	468	"env exists mcinitcmd && env exists secureboot "\
8526a58a	469	"&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
d7a4ddd3	470	"&& fsl_mc lazyapply dpl 0x580d00000;" \
1a9ce6e0	471	"run distro_bootcmd;run nor_bootcmd; " \
d7a4ddd3 WK	472	"env exists secureboot && esbc_halt;"
	473	#endif
	474
1f55a938	475	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
e60476a0	476	#define CONFIG_FSL_MEMAC
e60476a0 PK	477	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	478	#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
	479	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	480	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	481
cf7ee6c4 PK	482	#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
	483	#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
	484	#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
	485	#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
	486	#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
	487	#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
	488	#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
	489	#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
	490	#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
	491	#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
	492	#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
	493	#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
	494	#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
	495	#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
	496	#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
	497	#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
	498
7ad9cc96	499	#define CONFIG_ETHPRIME "DPMAC1@xgmii"
e60476a0 PK	500
	501	#endif
	502
fcfdb6d5 SJ	503	#include <asm/fsl_secure_boot.h>
fcfdb6d5 SJ	504
7288c2c2	505	#endif /* __LS2_QDS_H */