[people/ms/u-boot.git] / include / configs / ls2085aqds.h

/*
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS2_QDS_H
#define __LS2_QDS_H

#include "ls2085a_common.h"

#define CONFIG_DISPLAY_BOARDINFO

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#define CONFIG_FSL_CLK
#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)

#define CONFIG_DDR_SPD
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS3	0x53
#define SPD_EEPROM_ADDRESS4	0x54
#define SPD_EEPROM_ADDRESS5	0x55
#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR		2
#define CONFIG_CHIP_SELECTS_PER_CTRL		4
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */

/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1a) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
					 CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif

#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2


#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH		0x06
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RCW_SRC_NAND		0x107
#define	QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_CSPR3_EXT	(0x0)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3		0x0

#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		(896 * 1024)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_SPL_PAD_TO		0x20000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x2000
#endif

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL

/* MC firmware */
#define CONFIG_SYS_LS_MC_FW_IN_NOR
#define CONFIG_SYS_LS_MC_FW_ADDR	0x580300000ULL

#define CONFIG_SYS_LS_MC_DPL_IN_NOR
#define CONFIG_SYS_LS_MC_DPL_ADDR	0x580700000ULL

#define CONFIG_SYS_LS_MC_DPC_IN_NOR
#define CONFIG_SYS_LS_MC_DPC_ADDR	0x580800000ULL

#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR	0x580900000ULL

/*
 * I2C
 */
#define I2C_MUX_PCA_ADDR		0x77
#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT      0x8

/* SPI */
#ifdef CONFIG_FSL_DSPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_EON
#endif

/*
 * MMC
 */
#ifdef CONFIG_MMC
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
#endif

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS3231               1
#define CONFIG_SYS_I2C_RTC_ADDR         0x68
#define CONFIG_CMD_DATE

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

#define CONFIG_FSL_MEMAC
#define CONFIG_PCI		/* Enable PCIE */
#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */

#ifdef CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif

/*  MMC  */
#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif

/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581100000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x28000000\0"

#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
#define	CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
#define	CONFIG_CMD_MII
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F

#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf

#define CONFIG_MII		/* MII PHY management */
#define CONFIG_ETHPRIME		"DPNI1"
#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */

#endif

/*
 * USB
 */
#define CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_EXT2

#endif /* __LS2_QDS_H */
Commit	Line	Data
7288c2c2 YS	1	/*
	2	* Copyright 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS2_QDS_H
	8	#define __LS2_QDS_H
	9
	10	#include "ls2085a_common.h"
7288c2c2	11
7288c2c2 YS	12	#define CONFIG_DISPLAY_BOARDINFO
	13
	14	#ifndef __ASSEMBLY__
	15	unsigned long get_board_sys_clk(void);
	16	unsigned long get_board_ddr_clk(void);
	17	#endif
	18
677f970b	19	#define CONFIG_FSL_CLK
7288c2c2 YS	20	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
	21	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
	22	#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
	23
	24	#define CONFIG_DDR_SPD
	25	#define CONFIG_DDR_ECC
	26	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	27	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	28	#define SPD_EEPROM_ADDRESS1 0x51
	29	#define SPD_EEPROM_ADDRESS2 0x52
	30	#define SPD_EEPROM_ADDRESS3 0x53
	31	#define SPD_EEPROM_ADDRESS4 0x54
	32	#define SPD_EEPROM_ADDRESS5 0x55
	33	#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
	34	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
	35	#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
	36	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	37	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	38	#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
	39	#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
	40
	41	/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
	42
	43	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	44	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	45	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(6410241024)
	46
	47	#define CONFIG_SYS_NOR0_CSPR \
	48	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	49	CSPR_PORT_SIZE_16 \| \
	50	CSPR_MSEL_NOR \| \
	51	CSPR_V)
	52	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	53	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	54	CSPR_PORT_SIZE_16 \| \
	55	CSPR_MSEL_NOR \| \
	56	CSPR_V)
	57	#define CONFIG_SYS_NOR1_CSPR \
	58	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) \| \
	59	CSPR_PORT_SIZE_16 \| \
	60	CSPR_MSEL_NOR \| \
	61	CSPR_V)
	62	#define CONFIG_SYS_NOR1_CSPR_EARLY \
	63	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) \| \
	64	CSPR_PORT_SIZE_16 \| \
	65	CSPR_MSEL_NOR \| \
	66	CSPR_V)
	67	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	68	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	69	FTIM0_NOR_TEADC(0x5) \| \
	70	FTIM0_NOR_TEAHC(0x5))
	71	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	72	FTIM1_NOR_TRAD_NOR(0x1a) \|\
	73	FTIM1_NOR_TSEQRAD_NOR(0x13))
	74	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	75	FTIM2_NOR_TCH(0x4) \| \
	76	FTIM2_NOR_TWPH(0x0E) \| \
	77	FTIM2_NOR_TWP(0x1c))
	78	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	79	#define CONFIG_SYS_IFC_CCR 0x01000000
	80
	81	#ifndef CONFIG_SYS_NO_FLASH
	82	#define CONFIG_FLASH_CFI_DRIVER
	83	#define CONFIG_SYS_FLASH_CFI
84	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
85	#define CONFIG_SYS_FLASH_QUIET_TEST
86	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
87
88	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
89	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
90	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
91	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
92
93	#define CONFIG_SYS_FLASH_EMPTY_INFO
94	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
95	CONFIG_SYS_FLASH_BASE + 0x40000000}
96	#endif
97
98	#define CONFIG_NAND_FSL_IFC
99	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
100	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
101
102
103	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
104	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
105	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
106	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
107	\| CSPR_V)
108	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
109
110	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
111	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
112	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
113	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
114	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
115	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
116	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
117
118	#define CONFIG_SYS_NAND_ONFI_DETECTION
119
120	/* ONFI NAND Flash mode0 Timing Params */
121	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
122	FTIM0_NAND_TWP(0x18) \| \
123	FTIM0_NAND_TWCHT(0x07) \| \
124	FTIM0_NAND_TWH(0x0a))
125	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
126	FTIM1_NAND_TWBE(0x39) \| \
127	FTIM1_NAND_TRR(0x0e) \| \
128	FTIM1_NAND_TRP(0x18))
129	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
130	FTIM2_NAND_TREH(0x0a) \| \
131	FTIM2_NAND_TWHRE(0x1e))
132	#define CONFIG_SYS_NAND_FTIM3 0x0
133
134	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
135	#define CONFIG_SYS_MAX_NAND_DEVICE 1
136	#define CONFIG_MTD_NAND_VERIFY_WRITE
137	#define CONFIG_CMD_NAND
138
139	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
140
141	#define CONFIG_FSL_QIXIS /* use common QIXIS code */
142	#define QIXIS_LBMAP_SWITCH 0x06
143	#define QIXIS_LBMAP_MASK 0x0f
144	#define QIXIS_LBMAP_SHIFT 0
145	#define QIXIS_LBMAP_DFLTBANK 0x00
146	#define QIXIS_LBMAP_ALTBANK 0x04
b2d5ac59	147	#define QIXIS_LBMAP_NAND 0x09
7288c2c2 YS	148	#define QIXIS_RST_CTL_RESET 0x31
	149	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	150	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	151	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
b2d5ac59	152	#define QIXIS_RCW_SRC_NAND 0x107
7288c2c2 YS	153	#define QIXIS_RST_FORCE_MEM 0x01
	154
	155	#define CONFIG_SYS_CSPR3_EXT (0x0)
	156	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	157	\| CSPR_PORT_SIZE_8 \
	158	\| CSPR_MSEL_GPCM \
	159	\| CSPR_V)
	160	#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	161	\| CSPR_PORT_SIZE_8 \
	162	\| CSPR_MSEL_GPCM \
	163	\| CSPR_V)
	164
	165	#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
	166	#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
	167	/* QIXIS Timing parameters for IFC CS3 */
	168	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	169	FTIM0_GPCM_TEADC(0x0e) \| \
	170	FTIM0_GPCM_TEAHC(0x0e))
	171	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	172	FTIM1_GPCM_TRAD(0x3f))
	173	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	174	FTIM2_GPCM_TCH(0xf) \| \
	175	FTIM2_GPCM_TWP(0x3E))
	176	#define CONFIG_SYS_CS3_FTIM3 0x0
	177
b2d5ac59 SW	178	#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
	179	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	180	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
	181	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
	182	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	183	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	184	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	185	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	186	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	187	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	188	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
	189	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
	190	#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
	191	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
	192	#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
	193	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	194	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	195	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	196	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	197	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	198	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	199	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	200	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	201	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	202	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	203	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	204	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	205	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	206
	207	#define CONFIG_ENV_IS_IN_NAND
	208	#define CONFIG_ENV_OFFSET (896 * 1024)
	209	#define CONFIG_ENV_SECT_SIZE 0x20000
	210	#define CONFIG_ENV_SIZE 0x2000
	211	#define CONFIG_SPL_PAD_TO 0x20000
	212	#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
	213	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
	214	#else
7288c2c2 YS	215	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	216	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	217	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	218	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	219	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	220	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	221	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	222	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	223	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	224	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	225	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
	226	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
	227	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
	228	#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
	229	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	230	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	231	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	232	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	233	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	234	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	235	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	236	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	237	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	238	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	239	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	240	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	241	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	242
b2d5ac59 SW	243	#define CONFIG_ENV_IS_IN_FLASH
	244	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
	245	#define CONFIG_ENV_SECT_SIZE 0x20000
	246	#define CONFIG_ENV_SIZE 0x2000
	247	#endif
	248
7288c2c2 YS	249	/* Debug Server firmware */
	250	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	251	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
	252
	253	/* MC firmware */
	254	#define CONFIG_SYS_LS_MC_FW_IN_NOR
	255	#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL
	256
	257	#define CONFIG_SYS_LS_MC_DPL_IN_NOR
	258	#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL
	259
	260	#define CONFIG_SYS_LS_MC_DPC_IN_NOR
	261	#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL
	262
	263	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
c1000c12 GR	264	#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
c1000c12 GR	265	#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL
7288c2c2 YS	266
	267	/*
	268	* I2C
	269	*/
	270	#define I2C_MUX_PCA_ADDR 0x77
	271	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
	272
	273	/* I2C bus multiplexer */
	274	#define I2C_MUX_CH_DEFAULT 0x8
	275
b7774b05 HW	276	/* SPI */
	277	#ifdef CONFIG_FSL_DSPI
	278	#define CONFIG_CMD_SF
	279	#define CONFIG_SPI_FLASH
	280	#define CONFIG_SPI_FLASH_STMICRO
	281	#define CONFIG_SPI_FLASH_SST
	282	#define CONFIG_SPI_FLASH_EON
	283	#endif
	284
8b06460e YL	285	/*
	286	* MMC
	287	*/
	288	#ifdef CONFIG_MMC
	289	#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
	290	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
	291	#endif
	292
7288c2c2 YS	293	/*
	294	* RTC configuration
	295	*/
	296	#define RTC
	297	#define CONFIG_RTC_DS3231 1
	298	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
6581440c	299	#define CONFIG_CMD_DATE
7288c2c2 YS	300
	301	/* EEPROM */
	302	#define CONFIG_ID_EEPROM
	303	#define CONFIG_CMD_EEPROM
	304	#define CONFIG_SYS_I2C_EEPROM_NXID
	305	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	306	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	307	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	308	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	309	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	310
7288c2c2 YS	311	#define CONFIG_FSL_MEMAC
	312	#define CONFIG_PCI /* Enable PCIE */
	313	#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
	314
	315	#ifdef CONFIG_PCI
7288c2c2	316	#define CONFIG_PCI_PNP
7288c2c2 YS	317	#define CONFIG_PCI_SCAN_SHOW
7288c2c2 YS	318	#define CONFIG_CMD_PCI
7288c2c2 YS	319	#endif
7288c2c2 YS	320
8b06460e YL	321	/* MMC */
	322	#define CONFIG_MMC
	323	#ifdef CONFIG_MMC
	324	#define CONFIG_CMD_MMC
	325	#define CONFIG_FSL_ESDHC
	326	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
	327	#define CONFIG_GENERIC_MMC
	328	#define CONFIG_CMD_FAT
	329	#define CONFIG_DOS_PARTITION
	330	#endif
7288c2c2 YS	331
	332	/* Initial environment variables */
	333	#undef CONFIG_EXTRA_ENV_SETTINGS
	334	#define CONFIG_EXTRA_ENV_SETTINGS \
	335	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	336	"loadaddr=0x80100000\0" \
	337	"kernel_addr=0x100000\0" \
	338	"ramdisk_addr=0x800000\0" \
	339	"ramdisk_size=0x2000000\0" \
	340	"fdt_high=0xa0000000\0" \
	341	"initrd_high=0xffffffffffffffff\0" \
	342	"kernel_start=0x581100000\0" \
	343	"kernel_load=0xa0000000\0" \
97421bd2	344	"kernel_size=0x28000000\0"
7288c2c2	345
e60476a0 PK	346	#ifdef CONFIG_FSL_MC_ENET
	347	#define CONFIG_FSL_MEMAC
	348	#define CONFIG_PHYLIB
	349	#define CONFIG_PHYLIB_10G
	350	#define CONFIG_CMD_MII
	351	#define CONFIG_PHY_VITESSE
	352	#define CONFIG_PHY_REALTEK
	353	#define CONFIG_PHY_TERANETICS
	354	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	355	#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
	356	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	357	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	358
cf7ee6c4 PK	359	#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
	360	#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
	361	#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
	362	#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
	363	#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
	364	#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
	365	#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
	366	#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
	367	#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
	368	#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
	369	#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
	370	#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
	371	#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
	372	#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
	373	#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
	374	#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
	375
e60476a0 PK	376	#define CONFIG_MII /* MII PHY management */
	377	#define CONFIG_ETHPRIME "DPNI1"
	378	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
	379
	380	#endif
	381
94e8cd80 NB	382	/*
	383	* USB
	384	*/
	385	#define CONFIG_HAS_FSL_XHCI_USB
	386	#define CONFIG_USB_XHCI
	387	#define CONFIG_USB_XHCI_FSL
	388	#define CONFIG_USB_XHCI_DWC3
	389	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	390	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
	391	#define CONFIG_CMD_USB
	392	#define CONFIG_USB_STORAGE
	393	#define CONFIG_CMD_EXT2
	394
7288c2c2	395	#endif /* __LS2_QDS_H */