[people/ms/u-boot.git] / include / configs / lubbock.h

/*
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the LUBBOCK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
#define CONFIG_LUBBOCK		1	/* on an LUBBOCK Board	    */
#define CONFIG_LCD		1
#ifdef CONFIG_LCD
#define CONFIG_SHARP_LM8V31
#endif
#define CONFIG_MMC
#define BOARD_LATE_INIT		1
#define CONFIG_DOS_PARTITION
#define	CONFIG_SYS_TEXT_BASE	0x0
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)

/*
 * Hardware drivers
 */
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x0C000000

/*
 * select serial console configuration
 */
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_FAT


#define CONFIG_BOOTDELAY	3
#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.0.0
#define CONFIG_IPADDR		192.168.0.21
#define CONFIG_SERVERIP		192.168.0.250
#define CONFIG_BOOTCOMMAND	"bootm 80000"
#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
#define CONFIG_CMDLINE_TAG
#define CONFIG_TIMESTAMP

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER		1
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
#else
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
#endif
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_DEVICE_NULLDEV	1

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */

						/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#ifdef CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE		0xF0000000
#endif

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */

#define CONFIG_SYS_DRAM_BASE		0xa0000000
#define CONFIG_SYS_DRAM_SIZE		0x04000000

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)

#define FPGA_REGS_BASE_PHYSICAL 0x08000000

/*
 * GPIO settings
 */
#define CONFIG_SYS_GPSR0_VAL		0x00008000
#define CONFIG_SYS_GPSR1_VAL		0x00FC0382
#define CONFIG_SYS_GPSR2_VAL		0x0001FFFF
#define CONFIG_SYS_GPCR0_VAL		0x00000000
#define CONFIG_SYS_GPCR1_VAL		0x00000000
#define CONFIG_SYS_GPCR2_VAL		0x00000000
#define CONFIG_SYS_GPDR0_VAL		0x0060A800
#define CONFIG_SYS_GPDR1_VAL		0x00FF0382
#define CONFIG_SYS_GPDR2_VAL		0x0001C000
#define CONFIG_SYS_GAFR0_L_VAL		0x98400000
#define CONFIG_SYS_GAFR0_U_VAL		0x00002950
#define CONFIG_SYS_GAFR1_L_VAL		0x000A9558
#define CONFIG_SYS_GAFR1_U_VAL		0x0005AAAA
#define CONFIG_SYS_GAFR2_L_VAL		0xA0000000
#define CONFIG_SYS_GAFR2_U_VAL		0x00000002

#define CONFIG_SYS_PSSR_VAL		0x20

#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
#define	CONFIG_SYS_CKEN			0x0

/*
 * Memory settings
 */
#define CONFIG_SYS_MSC0_VAL		0x23F223F2
#define CONFIG_SYS_MSC1_VAL		0x3FF1A441
#define CONFIG_SYS_MSC2_VAL		0x7FF97FF1
#define CONFIG_SYS_MDCNFG_VAL		0x00001AC9
#define CONFIG_SYS_MDREFR_VAL		0x00018018
#define CONFIG_SYS_MDMRS_VAL		0x00000000

#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
#define	CONFIG_SYS_SXCNFG_VAL		0x00000000

/*
 * PCMCIA and CF Interfaces
 */
#define CONFIG_SYS_MECR_VAL		0x00000000
#define CONFIG_SYS_MCMEM0_VAL		0x00010504
#define CONFIG_SYS_MCMEM1_VAL		0x00010504
#define CONFIG_SYS_MCATT0_VAL		0x00010504
#define CONFIG_SYS_MCATT1_VAL		0x00010504
#define CONFIG_SYS_MCIO0_VAL		0x00004715
#define CONFIG_SYS_MCIO1_VAL		0x00004715

#define _LED			0x08000010
#define LED_BLANK		0x08000040

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */

/* NOTE: many default partitioning schemes assume the kernel starts at the
 * second sector, not an environment.  You have been warned!
 */
#define	CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
#define CONFIG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
#define CONFIG_ENV_SIZE		(PHYS_FLASH_SECT_SIZE / 16)


/*
 * FPGA Offsets
 */
#define WHOAMI_OFFSET		0x00
#define HEXLED_OFFSET		0x10
#define BLANKLED_OFFSET		0x40
#define DISCRETELED_OFFSET	0x40
#define CNFG_SWITCHES_OFFSET	0x50
#define USER_SWITCHES_OFFSET	0x60
#define MISC_WR_OFFSET		0x80
#define MISC_RD_OFFSET		0x90
#define INT_MASK_OFFSET		0xC0
#define INT_CLEAR_OFFSET	0xD0
#define GP_OFFSET		0x100

#endif	/* __CONFIG_H */
Commit	Line	Data
da27dcf0 WD	1	/*
	2	* (C) Copyright 2002
	3	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	*
	5	* (C) Copyright 2002
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* Configuation settings for the LUBBOCK board.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
71f95118	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
da27dcf0 WD	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
da27dcf0 WD	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
71f95118 WD	37	#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
	38	#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
	39	#define CONFIG_LCD 1
63cfcbb4 WD	40	#ifdef CONFIG_LCD
	41	#define CONFIG_SHARP_LM8V31
	42	#endif
b03d92e5	43	#define CONFIG_MMC
c837dcb1	44	#define BOARD_LATE_INIT 1
10cdb8db	45	#define CONFIG_DOS_PARTITION
3c43ca2a	46	#define CONFIG_SYS_TEXT_BASE 0x0
71f95118	47	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
da27dcf0	48
b3acb6cd	49	/* we will never enable dcache, because we have to setup MMU first */
e47f2db5	50	#define CONFIG_SYS_DCACHE_OFF
b3acb6cd	51
da27dcf0 WD	52	/*
	53	* Size of malloc() pool
	54	*/
6d0f6bcf	55	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
da27dcf0 WD	56
	57	/*
	58	* Hardware drivers
	59	*/
ac6b362a	60	#define CONFIG_LAN91C96
45219c46	61	#define CONFIG_LAN91C96_BASE 0x0C000000
da27dcf0 WD	62
	63	/*
	64	* select serial console configuration
	65	*/
379be585	66	#define CONFIG_PXA_SERIAL
71f95118	67	#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
da27dcf0 WD	68
	69	/* allow to overwrite serial and ethaddr */
	70	#define CONFIG_ENV_OVERWRITE
	71
71f95118	72	#define CONFIG_BAUDRATE 115200
da27dcf0	73
da27dcf0	74
7f5c0157 JL	75	/*
	76	* BOOTP options
	77	*/
	78	#define CONFIG_BOOTP_BOOTFILESIZE
	79	#define CONFIG_BOOTP_BOOTPATH
	80	#define CONFIG_BOOTP_GATEWAY
	81	#define CONFIG_BOOTP_HOSTNAME
	82
	83
9bbb1c08 JL	84	/*
	85	* Command line configuration.
	86	*/
	87	#include <config_cmd_default.h>
	88
9bbb1c08 JL	89	#define CONFIG_CMD_FAT
9bbb1c08 JL	90
da27dcf0	91
71f95118 WD	92	#define CONFIG_BOOTDELAY 3
	93	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	94	#define CONFIG_NETMASK 255.255.0.0
	95	#define CONFIG_IPADDR 192.168.0.21
	96	#define CONFIG_SERVERIP 192.168.0.250
f2af3eb5	97	#define CONFIG_BOOTCOMMAND "bootm 80000"
71f95118 WD	98	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
71f95118 WD	99	#define CONFIG_CMDLINE_TAG
f2af3eb5	100	#define CONFIG_TIMESTAMP
da27dcf0	101
9bbb1c08	102	#if defined(CONFIG_CMD_KGDB)
71f95118 WD	103	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
71f95118 WD	104	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
da27dcf0 WD	105	#endif
	106
	107	/*
	108	* Miscellaneous configurable options
	109	*/
6d0f6bcf JCPV	110	#define CONFIG_SYS_HUSH_PARSER 1
6d0f6bcf JCPV	111	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
71f95118	112
6d0f6bcf JCPV	113	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	114	#ifdef CONFIG_SYS_HUSH_PARSER
	115	#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
71f95118	116	#else
6d0f6bcf	117	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
71f95118	118	#endif
6d0f6bcf JCPV	119	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	120	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	121	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	122	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	123	#define CONFIG_SYS_DEVICE_NULLDEV 1
71f95118	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
6d0f6bcf JCPV	126	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
da27dcf0	127
6d0f6bcf	128	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
da27dcf0	129
94a33129	130	#define CONFIG_SYS_HZ 1000
6d0f6bcf	131	#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
da27dcf0	132
71f95118	133	/* valid baudrates */
6d0f6bcf	134	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
da27dcf0	135
b03d92e5 JCPV	136	#ifdef CONFIG_MMC
	137	#define CONFIG_PXA_MMC
	138	#define CONFIG_CMD_MMC
6d0f6bcf	139	#define CONFIG_SYS_MMC_BASE 0xF0000000
b03d92e5	140	#endif
da27dcf0 WD	141
	142	/*
	143	* Stack sizes
	144	*
	145	* The stack sizes are set up in start.S using the settings below
	146	*/
71f95118	147	#define CONFIG_STACKSIZE (1281024) / regular stack */
da27dcf0	148	#ifdef CONFIG_USE_IRQ
71f95118 WD	149	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
71f95118 WD	150	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
da27dcf0 WD	151	#endif
	152
	153	/*
	154	* Physical Memory Map
	155	*/
71f95118 WD	156	#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
	157	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	158	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	159	#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
	160	#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
	161	#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
	162	#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
	163	#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
	164	#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
	165
	166	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	167	#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
	168	#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
	169	#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
	170	#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
	171
6d0f6bcf JCPV	172	#define CONFIG_SYS_DRAM_BASE 0xa0000000
6d0f6bcf JCPV	173	#define CONFIG_SYS_DRAM_SIZE 0x04000000
71f95118	174
6d0f6bcf	175	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
da27dcf0	176
6ef6eb91	177	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
25ddd1fb	178	#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
6ef6eb91	179
da27dcf0 WD	180	#define FPGA_REGS_BASE_PHYSICAL 0x08000000
	181
	182	/*
	183	* GPIO settings
	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_GPSR0_VAL 0x00008000
	186	#define CONFIG_SYS_GPSR1_VAL 0x00FC0382
	187	#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF
	188	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	189	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	190	#define CONFIG_SYS_GPCR2_VAL 0x00000000
	191	#define CONFIG_SYS_GPDR0_VAL 0x0060A800
	192	#define CONFIG_SYS_GPDR1_VAL 0x00FF0382
	193	#define CONFIG_SYS_GPDR2_VAL 0x0001C000
	194	#define CONFIG_SYS_GAFR0_L_VAL 0x98400000
	195	#define CONFIG_SYS_GAFR0_U_VAL 0x00002950
	196	#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558
	197	#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
	198	#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
	199	#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
	200
	201	#define CONFIG_SYS_PSSR_VAL 0x20
da27dcf0	202
3c43ca2a MV	203	#define CONFIG_SYS_CCCR CCCR_L27\|CCCR_M2\|CCCR_N10
	204	#define CONFIG_SYS_CKEN 0x0
	205
da27dcf0 WD	206	/*
	207	* Memory settings
	208	*/
6d0f6bcf JCPV	209	#define CONFIG_SYS_MSC0_VAL 0x23F223F2
	210	#define CONFIG_SYS_MSC1_VAL 0x3FF1A441
	211	#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
	212	#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
	213	#define CONFIG_SYS_MDREFR_VAL 0x00018018
	214	#define CONFIG_SYS_MDMRS_VAL 0x00000000
da27dcf0	215
3c43ca2a MV	216	#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
	217	#define CONFIG_SYS_SXCNFG_VAL 0x00000000
	218
da27dcf0 WD	219	/*
	220	* PCMCIA and CF Interfaces
	221	*/
6d0f6bcf JCPV	222	#define CONFIG_SYS_MECR_VAL 0x00000000
	223	#define CONFIG_SYS_MCMEM0_VAL 0x00010504
	224	#define CONFIG_SYS_MCMEM1_VAL 0x00010504
	225	#define CONFIG_SYS_MCATT0_VAL 0x00010504
	226	#define CONFIG_SYS_MCATT1_VAL 0x00010504
	227	#define CONFIG_SYS_MCIO0_VAL 0x00004715
	228	#define CONFIG_SYS_MCIO1_VAL 0x00004715
da27dcf0	229
71f95118 WD	230	#define _LED 0x08000010
71f95118 WD	231	#define LED_BLANK 0x08000040
da27dcf0 WD	232
	233	/*
	234	* FLASH and environment organization
	235	*/
6d0f6bcf JCPV	236	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	237	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
da27dcf0 WD	238
da27dcf0 WD	239	/* timeout values are in ticks */
6d0f6bcf JCPV	240	#define CONFIG_SYS_FLASH_ERASE_TOUT (25CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	241	#define CONFIG_SYS_FLASH_WRITE_TOUT (25CONFIG_SYS_HZ) / Timeout for Flash Write */
da27dcf0	242
f2af3eb5 WD	243	/* NOTE: many default partitioning schemes assume the kernel starts at the
	244	* second sector, not an environment. You have been warned!
	245	*/
6d0f6bcf	246	#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
5a1aceb0	247	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	248	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
	249	#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
	250	#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
da27dcf0 WD	251
	252
	253	/*
	254	* FPGA Offsets
	255	*/
71f95118 WD	256	#define WHOAMI_OFFSET 0x00
	257	#define HEXLED_OFFSET 0x10
	258	#define BLANKLED_OFFSET 0x40
	259	#define DISCRETELED_OFFSET 0x40
	260	#define CNFG_SWITCHES_OFFSET 0x50
	261	#define USER_SWITCHES_OFFSET 0x60
	262	#define MISC_WR_OFFSET 0x80
	263	#define MISC_RD_OFFSET 0x90
	264	#define INT_MASK_OFFSET 0xC0
	265	#define INT_CLEAR_OFFSET 0xD0
	266	#define GP_OFFSET 0x100
	267
	268	#endif /* __CONFIG_H */