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1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * Configuation settings for the LUBBOCK board. | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
71f95118 | 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
da27dcf0 WD |
22 | * GNU General Public License for more details. |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * If we are developing, we might want to start armboot from ram | |
35 | * so we MUST NOT initialize critical regs like mem-timing ... | |
36 | */ | |
71f95118 | 37 | #define CONFIG_INIT_CRITICAL /* undef for developing */ |
da27dcf0 WD |
38 | |
39 | /* | |
40 | * High Level Configuration Options | |
41 | * (easy to change) | |
42 | */ | |
71f95118 WD |
43 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ |
44 | #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ | |
45 | #define CONFIG_LCD 1 | |
46 | #define CONFIG_MMC 1 | |
47 | #define BOARD_POST_INIT 1 | |
da27dcf0 | 48 | |
71f95118 | 49 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
da27dcf0 WD |
50 | |
51 | /* | |
52 | * Size of malloc() pool | |
53 | */ | |
71f95118 | 54 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
a8c7c708 | 55 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
da27dcf0 WD |
56 | |
57 | /* | |
58 | * Hardware drivers | |
59 | */ | |
45219c46 WD |
60 | #define CONFIG_DRIVER_LAN91C96 |
61 | #define CONFIG_LAN91C96_BASE 0x0C000000 | |
da27dcf0 WD |
62 | |
63 | /* | |
64 | * select serial console configuration | |
65 | */ | |
71f95118 | 66 | #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ |
da27dcf0 WD |
67 | |
68 | /* allow to overwrite serial and ethaddr */ | |
69 | #define CONFIG_ENV_OVERWRITE | |
70 | ||
71f95118 | 71 | #define CONFIG_BAUDRATE 115200 |
da27dcf0 | 72 | |
71f95118 | 73 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) |
da27dcf0 WD |
74 | |
75 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
76 | #include <cmd_confdefs.h> | |
77 | ||
71f95118 WD |
78 | #define CONFIG_BOOTDELAY 3 |
79 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b | |
80 | #define CONFIG_NETMASK 255.255.0.0 | |
81 | #define CONFIG_IPADDR 192.168.0.21 | |
82 | #define CONFIG_SERVERIP 192.168.0.250 | |
83 | #define CONFIG_BOOTCOMMAND "bootm 40000" | |
84 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" | |
85 | #define CONFIG_CMDLINE_TAG | |
da27dcf0 WD |
86 | |
87 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
71f95118 WD |
88 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
89 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
da27dcf0 WD |
90 | #endif |
91 | ||
92 | /* | |
93 | * Miscellaneous configurable options | |
94 | */ | |
71f95118 WD |
95 | #define CFG_HUSH_PARSER 1 |
96 | #define CFG_PROMPT_HUSH_PS2 "> " | |
97 | ||
98 | #define CFG_LONGHELP /* undef to save memory */ | |
99 | #ifdef CFG_HUSH_PARSER | |
100 | #define CFG_PROMPT "$ " /* Monitor Command Prompt */ | |
101 | #else | |
102 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
103 | #endif | |
104 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
da27dcf0 | 105 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
71f95118 WD |
106 | #define CFG_MAXARGS 16 /* max number of command args */ |
107 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
108 | #define CFG_DEVICE_NULLDEV 1 | |
109 | ||
110 | #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ | |
111 | #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
da27dcf0 | 112 | |
71f95118 | 113 | #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
da27dcf0 | 114 | |
71f95118 | 115 | #define CFG_LOAD_ADDR 0xa8000000 /* default load address */ |
da27dcf0 | 116 | |
71f95118 WD |
117 | #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
118 | #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ | |
da27dcf0 | 119 | |
71f95118 WD |
120 | /* valid baudrates */ |
121 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
da27dcf0 | 122 | |
71f95118 | 123 | #define CFG_MMC_BASE 0xF0000000 |
da27dcf0 WD |
124 | |
125 | /* | |
126 | * Stack sizes | |
127 | * | |
128 | * The stack sizes are set up in start.S using the settings below | |
129 | */ | |
71f95118 | 130 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
da27dcf0 | 131 | #ifdef CONFIG_USE_IRQ |
71f95118 WD |
132 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
133 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
da27dcf0 WD |
134 | #endif |
135 | ||
136 | /* | |
137 | * Physical Memory Map | |
138 | */ | |
71f95118 WD |
139 | #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ |
140 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
141 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
142 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | |
143 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
144 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | |
145 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
146 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | |
147 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
148 | ||
149 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
150 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ | |
151 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
152 | #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ | |
153 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ | |
154 | ||
155 | #define CFG_DRAM_BASE 0xa0000000 | |
156 | #define CFG_DRAM_SIZE 0x04000000 | |
157 | ||
158 | #define CFG_FLASH_BASE PHYS_FLASH_1 | |
da27dcf0 WD |
159 | |
160 | #define FPGA_REGS_BASE_PHYSICAL 0x08000000 | |
161 | ||
162 | /* | |
163 | * GPIO settings | |
164 | */ | |
71f95118 WD |
165 | #define CFG_GPSR0_VAL 0x00008000 |
166 | #define CFG_GPSR1_VAL 0x00FC0382 | |
167 | #define CFG_GPSR2_VAL 0x0001FFFF | |
168 | #define CFG_GPCR0_VAL 0x00000000 | |
169 | #define CFG_GPCR1_VAL 0x00000000 | |
170 | #define CFG_GPCR2_VAL 0x00000000 | |
171 | #define CFG_GPDR0_VAL 0x0060A800 | |
172 | #define CFG_GPDR1_VAL 0x00FF0382 | |
173 | #define CFG_GPDR2_VAL 0x0001C000 | |
174 | #define CFG_GAFR0_L_VAL 0x98400000 | |
175 | #define CFG_GAFR0_U_VAL 0x00002950 | |
176 | #define CFG_GAFR1_L_VAL 0x000A9558 | |
177 | #define CFG_GAFR1_U_VAL 0x0005AAAA | |
178 | #define CFG_GAFR2_L_VAL 0xA0000000 | |
179 | #define CFG_GAFR2_U_VAL 0x00000002 | |
180 | ||
181 | #define CFG_PSSR_VAL 0x20 | |
da27dcf0 WD |
182 | |
183 | /* | |
184 | * Memory settings | |
185 | */ | |
71f95118 WD |
186 | #define CFG_MSC0_VAL 0x23F223F2 |
187 | #define CFG_MSC1_VAL 0x3FF1A441 | |
188 | #define CFG_MSC2_VAL 0x7FF97FF1 | |
189 | #define CFG_MDCNFG_VAL 0x00001AC9 | |
190 | #define CFG_MDREFR_VAL 0x00018018 | |
191 | #define CFG_MDMRS_VAL 0x00000000 | |
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192 | |
193 | /* | |
194 | * PCMCIA and CF Interfaces | |
195 | */ | |
71f95118 WD |
196 | #define CFG_MECR_VAL 0x00000000 |
197 | #define CFG_MCMEM0_VAL 0x00010504 | |
198 | #define CFG_MCMEM1_VAL 0x00010504 | |
199 | #define CFG_MCATT0_VAL 0x00010504 | |
200 | #define CFG_MCATT1_VAL 0x00010504 | |
201 | #define CFG_MCIO0_VAL 0x00004715 | |
202 | #define CFG_MCIO1_VAL 0x00004715 | |
da27dcf0 | 203 | |
71f95118 WD |
204 | #define _LED 0x08000010 |
205 | #define LED_BLANK 0x08000040 | |
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206 | |
207 | /* | |
208 | * FLASH and environment organization | |
209 | */ | |
71f95118 WD |
210 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
211 | #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
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212 | |
213 | /* timeout values are in ticks */ | |
71f95118 WD |
214 | #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ |
215 | #define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ | |
da27dcf0 WD |
216 | |
217 | /* FIXME */ | |
71f95118 WD |
218 | #define CFG_ENV_IS_IN_FLASH 1 |
219 | #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ | |
220 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
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221 | |
222 | ||
223 | /* | |
224 | * FPGA Offsets | |
225 | */ | |
71f95118 WD |
226 | #define WHOAMI_OFFSET 0x00 |
227 | #define HEXLED_OFFSET 0x10 | |
228 | #define BLANKLED_OFFSET 0x40 | |
229 | #define DISCRETELED_OFFSET 0x40 | |
230 | #define CNFG_SWITCHES_OFFSET 0x50 | |
231 | #define USER_SWITCHES_OFFSET 0x60 | |
232 | #define MISC_WR_OFFSET 0x80 | |
233 | #define MISC_RD_OFFSET 0x90 | |
234 | #define INT_MASK_OFFSET 0xC0 | |
235 | #define INT_CLEAR_OFFSET 0xD0 | |
236 | #define GP_OFFSET 0x100 | |
237 | ||
238 | #endif /* __CONFIG_H */ |