[people/ms/u-boot.git] / include / configs / makalu.h

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * makalu.h - configuration for AMCC Makalu (405EX)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_MAKALU		1		/* Board is Makalu	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_405EX		1		/* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ	33330000	/* ext frequency to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFC000000
#define CFG_FPGA_BASE		0xF0000000
#define CFG_PERIPHERAL_BASE	0xEF600000      /* internal peripherals*/
#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc()	*/
#define CFG_MONITOR_BASE	(TEXT_BASE)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR	0x02000000	/* inside of SDRAM	*/
#define CFG_INIT_RAM_END	(4 << 10)
#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/* reserve some memory for POST and BOOT limit info */
#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 16)

/* extra data in init-ram */
#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
#define CFG_POST_MAGIC		(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
#define CFG_POST_VAL		(CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
#define CFG_OCM_DATA_ADDR	CFG_INIT_RAM_ADDR /* for commproc.c	*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK			/* no ext. clk		*/
#define CONFIG_BAUDRATE		115200
#define CONFIG_SERIAL_MULTI     1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE

#define CFG_BAUDRATE_TABLE						\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_FLASH_CFI			/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/

#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM	256

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
#define CFG_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/

/* Standard DTT sensor configuration */
#define CONFIG_DTT_DS1775	1
#define CONFIG_DTT_SENSORS	{ 0 }
#define CFG_I2C_DTT_ADDR	0x48

/* RTC configuration */
#define CONFIG_RTC_X1205	1
#define CFG_I2C_RTC_ADDR	0x6f

/*-----------------------------------------------------------------------
 * Ethernet
 *----------------------------------------------------------------------*/
#define CONFIG_M88E1111_PHY	1
#define CONFIG_IBM_EMAC4_V4	1
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		6	/* PHY address, See schematics	*/

#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0		1

#define CONFIG_NET_MULTI	1
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
#define CONFIG_PHY1_ADDR	0

#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"logversion=2\0"						\
	"netdev=eth0\0"							\
	"hostname=makalu\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"	\
	"net_nfs=tftp 200000 ${bootfile};"				\
		"run nfsargs addip addtty addmisc;"			\
		"bootm 200000\0"					\
	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
		"tftp ${fdt_addr} ${fdt_file};"				\
		"run nfsargs addip addtty addmisc;"			\
		"bootm 200000 - ${fdt_addr}\0"				\
	"flash_nfs=run nfsargs addip addtty addmisc;"			\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty addmisc;"			\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=makalu/uImage\0"					\
	"fdt_file=makalu/makalu.dtb\0"					\
	"fdt_addr=400000\0"						\
	"kernel_addr=fc000000\0"					\
	"ramdisk_addr=fc200000\0"					\
	"initrd_high=30000000\0"					\
	"load=tftp 200000 makalu/u-boot.bin\0"				\
	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
		"cp.b ${fileaddr} fffa0000 ${filesize};"		\
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	"pciconfighost=1\0"						\
	"pcie_mode=RP:RP\0"						\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate change	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_LOG
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP

/* POST support */
#define CONFIG_POST		(CFG_POST_MEMORY	| \
				 CFG_POST_CACHE		| \
				 CFG_POST_CPU		| \
				 CFG_POST_ETHER		| \
				 CFG_POST_I2C		| \
				 CFG_POST_MEMORY	| \
				 CFG_POST_UART)

/* Define here the base-addresses of the UARTs to test in POST */
#define CFG_POST_UART_TABLE	{UART0_BASE, UART1_BASE}

#define CONFIG_LOGBUFFER
#define CFG_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/

#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	        16	/* max number of command args	*/
#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *----------------------------------------------------------------------*/
#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
#define CONFIG_PCI_CONFIG_HOST_BRIDGE

/*-----------------------------------------------------------------------
 * PCIe stuff
 *----------------------------------------------------------------------*/
#define CFG_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
#define CFG_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */

#define	CFG_PCIE0_CFGBASE	0xa0000000      /* remote access */
#define	CFG_PCIE0_XCFGBASE	0xb0000000      /* local access */
#define	CFG_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */

#define	CFG_PCIE1_CFGBASE	0xc0000000      /* remote access */
#define	CFG_PCIE1_XCFGBASE	0xd0000000      /* local access */
#define	CFG_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */

#define	CFG_PCIE0_UTLBASE	0xef502000
#define	CFG_PCIE1_UTLBASE	0xef503000

/* base address of inbound PCIe window */
#define CFG_PCIE_INBOUND_BASE	0x0000000000000000ULL

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
/* Memory Bank 0 (NOR-FLASH) initialization					*/
#define CFG_EBC_PB0AP		0x08033700
#define CFG_EBC_PB0CR		(CFG_FLASH_BASE | 0xda000)

/* Memory Bank 2 (CPLD) initialization						*/
#define CFG_EBC_PB2AP           0x9400C800
#define CFG_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit	*/

#define CFG_EBC_CFG		0x7FC00000 /*  EBC0_CFG */

/*-----------------------------------------------------------------------
 * GPIO Setup
 *----------------------------------------------------------------------*/
#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
{											\
/* GPIO Core 0 */									\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0	EBC_DATA_PAR(0)			*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1	EBC_DATA_PAR(1)			*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2	EBC_DATA_PAR(2)			*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3	EBC_DATA_PAR(3)			*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4	EBC_DATA(20)	USB2_DATA(4)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5	EBC_DATA(21)	USB2_DATA(5)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6	EBC_DATA(22)	USB2_DATA(6)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7	EBC_DATA(23)	USB2_DATA(7)	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	CS(1)/NFCE(1)	IRQ(7)		*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	CS(2)/NFCE(2)	IRQ(8)		*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)	IRQ(9)		*/	\
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6)				*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)	USB2_DATA(0)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)	USB2_DATA(1)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)	USB2_DATA(2)	*/	\
{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)	USB2_DATA(3)	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD	UART1_CTS	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR	UART1_RTS	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS			*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS			*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO20 UART0_DTR	UART1_TX	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO21 UART0_RI	UART1_RX	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ	DMA_ACK2	*/	\
{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK	DMA_REQ2	*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ	DMA_EOT2	IRQ(4) */ \
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK	DMA_ACK3	IRQ(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)	DMA_EOT0	TS(3) */ \
{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ	DMA_EOT3	IRQ(5) */ \
{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO28				*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO29 DMA_EOT1	IRQ(2)		*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1	IRQ(1)		*/	\
{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1	IRQ(0)		*/	\
}												\
}

#define CFG_GPIO_PCIE_RST	23
#define CFG_GPIO_PCIE_CLKREQ	27
#define CFG_GPIO_PCIE_WAKE	28

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#endif	/* __CONFIG_H */
Commit	Line	Data
211ea91a SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/************************************************************************
	25	* makalu.h - configuration for AMCC Makalu (405EX)
	26	***********************************************************************/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*-----------------------------------------------------------------------
	32	* High Level Configuration Options
	33	----------------------------------------------------------------------/
	34	#define CONFIG_MAKALU 1 /* Board is Makalu */
	35	#define CONFIG_4xx 1 /* ... PPC4xx family */
	36	#define CONFIG_405EX 1 /* Specifc 405EX support*/
	37	#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
	38
	39	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	40	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	41
	42	/*-----------------------------------------------------------------------
	43	* Base addresses -- Note these are effective addresses where the
	44	* actual resources get mapped (not physical addresses)
	45	----------------------------------------------------------------------/
	46	#define CFG_SDRAM_BASE 0x00000000
ecdcbd4f	47	#define CFG_FLASH_BASE 0xFC000000
211ea91a SR	48	#define CFG_FPGA_BASE 0xF0000000
	49	#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
	50	#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
ecdcbd4f	51	#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
211ea91a SR	52	#define CFG_MONITOR_BASE (TEXT_BASE)
	53
	54	/*-----------------------------------------------------------------------
	55	* Initial RAM & stack pointer
	56	----------------------------------------------------------------------/
	57	#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
	58	#define CFG_INIT_RAM_END (4 << 10)
	59	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
	60	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	61	/* reserve some memory for POST and BOOT limit info */
	62	#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
	63
	64	/* extra data in init-ram */
	65	#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
	66	#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
	67	#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
	68	#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
	69
	70	/*-----------------------------------------------------------------------
	71	* Serial Port
	72	----------------------------------------------------------------------/
	73	#undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */
	74	#define CONFIG_BAUDRATE 115200
	75	#define CONFIG_SERIAL_MULTI 1
	76	/* define this if you want console on UART1 */
	77	#undef CONFIG_UART1_CONSOLE
	78
	79	#define CFG_BAUDRATE_TABLE \
	80	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	81
	82	/*-----------------------------------------------------------------------
	83	* Environment
	84	----------------------------------------------------------------------/
	85	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	86
	87	/*-----------------------------------------------------------------------
	88	* FLASH related
	89	----------------------------------------------------------------------/
	90	#define CFG_FLASH_CFI /* The flash is CFI compatible */
	91	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
	92
	93	#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
	94	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	95	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	96
	97	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	98	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	99
	100	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	101	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	102
	103	#ifdef CFG_ENV_IS_IN_FLASH
	104	#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
	105	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	106	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	107
	108	/* Address and size of Redundant Environment Sector */
	109	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	110	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	111	#endif /* CFG_ENV_IS_IN_FLASH */
	112
	113	/*-----------------------------------------------------------------------
	114	* DDR SDRAM
	115	----------------------------------------------------------------------/
ecdcbd4f	116	#define CFG_MBYTES_SDRAM 256
211ea91a SR	117
	118	/*-----------------------------------------------------------------------
	119	* I2C
	120	----------------------------------------------------------------------/
	121	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	122	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	123	#define CFG_I2C_SLAVE 0x7F
	124
	125	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
	126	#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
	127	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	128
	129	/* Standard DTT sensor configuration */
	130	#define CONFIG_DTT_DS1775 1
	131	#define CONFIG_DTT_SENSORS { 0 }
	132	#define CFG_I2C_DTT_ADDR 0x48
	133
	134	/* RTC configuration */
	135	#define CONFIG_RTC_X1205 1
	136	#define CFG_I2C_RTC_ADDR 0x6f
	137
	138	/*-----------------------------------------------------------------------
	139	* Ethernet
	140	----------------------------------------------------------------------/
	141	#define CONFIG_M88E1111_PHY 1
	142	#define CONFIG_IBM_EMAC4_V4 1
	143	#define CONFIG_MII 1 /* MII PHY management */
	144	#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
	145
	146	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
	147	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	148
	149	#define CONFIG_HAS_ETH0 1
	150
	151	#define CONFIG_NET_MULTI 1
	152	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
ecdcbd4f	153	#define CONFIG_PHY1_ADDR 0
211ea91a SR	154
	155	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
	156
	157	#define CONFIG_PREBOOT "echo;" \
	158	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	159	"echo"
	160
	161	#undef CONFIG_BOOTARGS
	162
	163	#define CONFIG_EXTRA_ENV_SETTINGS \
	164	"logversion=2\0" \
	165	"netdev=eth0\0" \
	166	"hostname=makalu\0" \
	167	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	168	"nfsroot=${serverip}:${rootpath}\0" \
	169	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	170	"addip=setenv bootargs ${bootargs} " \
	171	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	172	":${hostname}:${netdev}:off panic=1\0" \
	173	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	174	"addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" \
	175	"net_nfs=tftp 200000 ${bootfile};" \
	176	"run nfsargs addip addtty addmisc;" \
	177	"bootm 200000\0" \
	178	"net_nfs_fdt=tftp 200000 ${bootfile};" \
	179	"tftp ${fdt_addr} ${fdt_file};" \
	180	"run nfsargs addip addtty addmisc;" \
	181	"bootm 200000 - ${fdt_addr}\0" \
	182	"flash_nfs=run nfsargs addip addtty addmisc;" \
	183	"bootm ${kernel_addr}\0" \
	184	"flash_self=run ramargs addip addtty addmisc;" \
	185	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	186	"rootpath=/opt/eldk/ppc_4xx\0" \
	187	"bootfile=makalu/uImage\0" \
	188	"fdt_file=makalu/makalu.dtb\0" \
	189	"fdt_addr=400000\0" \
ecdcbd4f SR	190	"kernel_addr=fc000000\0" \
ecdcbd4f SR	191	"ramdisk_addr=fc200000\0" \
211ea91a SR	192	"initrd_high=30000000\0" \
	193	"load=tftp 200000 makalu/u-boot.bin\0" \
	194	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
	195	"cp.b ${fileaddr} fffa0000 ${filesize};" \
	196	"setenv filesize;saveenv\0" \
	197	"upd=run load update\0" \
	198	"pciconfighost=1\0" \
	199	"pcie_mode=RP:RP\0" \
	200	""
	201	#define CONFIG_BOOTCOMMAND "run flash_self"
	202
	203	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	204
	205	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	206	#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
	207
	208	/*
	209	* BOOTP options
	210	*/
	211	#define CONFIG_BOOTP_BOOTFILESIZE
	212	#define CONFIG_BOOTP_BOOTPATH
	213	#define CONFIG_BOOTP_GATEWAY
	214	#define CONFIG_BOOTP_HOSTNAME
	215
	216	/*
	217	* Command line configuration.
	218	*/
	219	#include <config_cmd_default.h>
	220
	221	#define CONFIG_CMD_ASKENV
	222	#define CONFIG_CMD_DATE
	223	#define CONFIG_CMD_DHCP
	224	#define CONFIG_CMD_DIAG
	225	#define CONFIG_CMD_DTT
	226	#define CONFIG_CMD_EEPROM
	227	#define CONFIG_CMD_ELF
	228	#define CONFIG_CMD_I2C
	229	#define CONFIG_CMD_IRQ
	230	#define CONFIG_CMD_LOG
	231	#define CONFIG_CMD_MII
	232	#define CONFIG_CMD_NET
	233	#define CONFIG_CMD_NFS
	234	#define CONFIG_CMD_PCI
	235	#define CONFIG_CMD_PING
	236	#define CONFIG_CMD_REGINFO
afe9fa59	237	#define CONFIG_CMD_SNTP
211ea91a SR	238
	239	/* POST support */
	240	#define CONFIG_POST (CFG_POST_MEMORY \| \
	241	CFG_POST_CACHE \| \
	242	CFG_POST_CPU \| \
	243	CFG_POST_ETHER \| \
	244	CFG_POST_I2C \| \
	245	CFG_POST_MEMORY \| \
	246	CFG_POST_UART)
	247
	248	/* Define here the base-addresses of the UARTs to test in POST */
	249	#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
	250
	251	#define CONFIG_LOGBUFFER
	252	#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
	253
	254	#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
	255
	256	#undef CONFIG_WATCHDOG /* watchdog disabled */
	257
	258	/*-----------------------------------------------------------------------
	259	* Miscellaneous configurable options
	260	----------------------------------------------------------------------/
	261	#define CFG_LONGHELP /* undef to save memory */
	262	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	263	#if defined(CONFIG_CMD_KGDB)
	264	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	265	#else
	266	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	267	#endif
	268	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	269	#define CFG_MAXARGS 16 /* max number of command args */
	270	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	271
	272	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	273	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	274
	275	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	276	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	277
	278	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	279
	280	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	281	#define CONFIG_LOOPW 1 /* enable loopw command */
	282	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	283	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	284	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
ecdcbd4f	285	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
211ea91a SR	286
	287	/*-----------------------------------------------------------------------
	288	* PCI stuff
	289	----------------------------------------------------------------------/
	290	#define CONFIG_PCI /* include pci support */
	291	#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
	292	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
	293	#define CONFIG_PCI_CONFIG_HOST_BRIDGE
	294
	295	/*-----------------------------------------------------------------------
	296	* PCIe stuff
	297	----------------------------------------------------------------------/
	298	#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
	299	#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
	300
	301	#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
	302	#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
	303	#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
	304
	305	#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
	306	#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
	307	#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
	308
	309	#define CFG_PCIE0_UTLBASE 0xef502000
	310	#define CFG_PCIE1_UTLBASE 0xef503000
	311
	312	/* base address of inbound PCIe window */
	313	#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
	314
	315	/*
	316	* For booting Linux, the board info and command line data
	317	* have to be in the first 8 MB of memory, since this is
	318	* the maximum mapped by the Linux kernel during initialization.
	319	*/
	320	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	321
211ea91a SR	322	/*-----------------------------------------------------------------------
	323	* External Bus Controller (EBC) Setup
	324	----------------------------------------------------------------------/
	325	/* Memory Bank 0 (NOR-FLASH) initialization */
63362cfc	326	#define CFG_EBC_PB0AP 0x08033700
ecdcbd4f	327	#define CFG_EBC_PB0CR (CFG_FLASH_BASE \| 0xda000)
211ea91a SR	328
	329	/* Memory Bank 2 (CPLD) initialization */
	330	#define CFG_EBC_PB2AP 0x9400C800
	331	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
	332
	333	#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
	334
	335	/*-----------------------------------------------------------------------
	336	* GPIO Setup
	337	----------------------------------------------------------------------/
ecdcbd4f SR	338	#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
	339	{ \
	340	/* GPIO Core 0 */ \
	341	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
	342	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
	343	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
	344	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
7cfc12a7 SR	345	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
	346	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
	347	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
	348	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
8be76090 SR	349	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
	350	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
	351	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
ecdcbd4f	352	{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
7cfc12a7 SR	353	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
	354	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
	355	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
	356	{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
ecdcbd4f SR	357	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
	358	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
	359	{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
	360	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
	361	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
	362	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
	363	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
	364	{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
	365	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
	366	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
	367	{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
	368	{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
	369	{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \
8be76090 SR	370	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
	371	{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
	372	{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
ecdcbd4f SR	373	} \
	374	}
	375
	376	#define CFG_GPIO_PCIE_RST 23
	377	#define CFG_GPIO_PCIE_CLKREQ 27
	378	#define CFG_GPIO_PCIE_WAKE 28
211ea91a SR	379
	380	/*
	381	* Internal Definitions
	382	*
	383	* Boot Flags
	384	*/
	385	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	386	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	387
	388	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	389	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	390	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	391	#endif
	392
	393	/* pass open firmware flat tree */
	394	#define CONFIG_OF_LIBFDT 1
	395	#define CONFIG_OF_BOARD_SETUP 1
	396
211ea91a	397	#endif /* __CONFIG_H */