[people/ms/u-boot.git] / include / configs / maxbcm.h

/*
 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_DB_MV7846MP_GP_H
#define _CONFIG_DB_MV7846MP_GP_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_DISPLAY_BOARDINFO_LATE

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define	CONFIG_SYS_TEXT_BASE	0x00800000
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		1000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3

/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */

#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */

#define CONFIG_SYS_ALT_MEMTEST

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40004030
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endif

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

/* SPL related SPI defines */
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_DDR_FIXED_SIZE		(1 << 20)	/* 1GiB */
#define CONFIG_BOARD_ECC_SUPPORT	/* this board supports ECC */

#endif /* _CONFIG_DB_MV7846MP_GP_H */
Commit	Line	Data
a4884831 SR	1	/*
	2	* Copyright (C) 2014 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_DB_MV7846MP_GP_H
	8	#define _CONFIG_DB_MV7846MP_GP_H
	9
	10	/*
	11	* High Level Configuration Options (easy to change)
	12	*/
a4884831 SR	13	#define CONFIG_DISPLAY_BOARDINFO_LATE
a4884831 SR	14
2923c2d2 SR	15	/*
	16	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	17	* for DDR ECC byte filling in the SPL before loading the main
	18	* U-Boot into it.
	19	*/
	20	#define CONFIG_SYS_TEXT_BASE 0x00800000
a4884831 SR	21	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	22
	23	/*
	24	* Commands configuration
	25	*/
a4884831 SR	26
	27	/* I2C */
	28	#define CONFIG_SYS_I2C
	29	#define CONFIG_SYS_I2C_MVTWSI
dd82242b	30	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
a4884831 SR	31	#define CONFIG_SYS_I2C_SLAVE 0x0
	32	#define CONFIG_SYS_I2C_SPEED 100000
	33
	34	/* SPI NOR flash default params, used by sf commands */
	35	#define CONFIG_SF_DEFAULT_SPEED 1000000
	36	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
a4884831 SR	37
	38	/* Environment in SPI NOR flash */
	39	#define CONFIG_ENV_IS_IN_SPI_FLASH
	40	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	41	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	42	#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
	43
	44	#define CONFIG_PHY_MARVELL /* there is a marvell phy */
a4884831	45	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
a4884831	46
a4884831 SR	47	#define CONFIG_SYS_ALT_MEMTEST
	48
	49	/*
	50	* mv-common.h should be defined after CMD configs since it used them
	51	* to enable certain macros
	52	*/
	53	#include "mv-common.h"
	54
e7778ec1 SR	55	/*
	56	* Memory layout while starting into the bin_hdr via the
	57	* BootROM:
	58	*
	59	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	60	* 0x4000.4030 bin_hdr start address
	61	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	62	* 0x4007.fffc BootROM stack top
	63	*
	64	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	65	* L2 cache thus cannot be used.
	66	*/
	67
	68	/* SPL */
	69	/* Defines for SPL */
	70	#define CONFIG_SPL_FRAMEWORK
	71	#define CONFIG_SPL_TEXT_BASE 0x40004030
	72	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	73
	74	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	75	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	76
6451223a SR	77	#ifdef CONFIG_SPL_BUILD
	78	#define CONFIG_SYS_MALLOC_SIMPLE
	79	#endif
e7778ec1 SR	80
	81	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	82	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	83
e7778ec1	84	/* SPL related SPI defines */
e7778ec1	85	#define CONFIG_SPL_SPI_LOAD
e7778ec1 SR	86	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
	87
	88	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
e7778ec1	89	#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
698ffab2	90	#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
e7778ec1	91
a4884831	92	#endif /* _CONFIG_DB_MV7846MP_GP_H */