[people/ms/u-boot.git] / include / configs / maxbcm.h

/*
 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_DB_MV7846MP_GP_H
#define _CONFIG_DB_MV7846MP_GP_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_ARMADA_XP		/* SOC Family Name */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define	CONFIG_SYS_TEXT_BASE	0x00800000
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */
#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
#define CONFIG_CMD_TIME

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		1000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3

/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */

#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
#define CONFIG_PHY_ADDR			{ 0x0, 0x1, 0x2, 0x3 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_SGMII
#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
#define CONFIG_RESET_PHY_R

#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40004030
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endif

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT

/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS		0
#define CONFIG_SPL_SPI_CS		0
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_AXP
#define CONFIG_DDR_FIXED_SIZE		(1 << 20)	/* 1GiB */

#endif /* _CONFIG_DB_MV7846MP_GP_H */
Commit	Line	Data
a4884831 SR	1	/*
	2	* Copyright (C) 2014 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_DB_MV7846MP_GP_H
	8	#define _CONFIG_DB_MV7846MP_GP_H
	9
	10	/*
	11	* High Level Configuration Options (easy to change)
	12	*/
	13	#define CONFIG_ARMADA_XP /* SOC Family Name */
42cc034f	14	#ifdef CONFIG_SPL_BUILD
a4884831	15	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
42cc034f	16	#endif
a4884831 SR	17	#define CONFIG_DISPLAY_BOARDINFO_LATE
a4884831 SR	18
2923c2d2 SR	19	/*
	20	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	21	* for DDR ECC byte filling in the SPL before loading the main
	22	* U-Boot into it.
	23	*/
	24	#define CONFIG_SYS_TEXT_BASE 0x00800000
a4884831 SR	25	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	26
	27	/*
	28	* Commands configuration
	29	*/
	30	#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
a4884831 SR	31	#define CONFIG_CMD_DHCP
	32	#define CONFIG_CMD_ENV
	33	#define CONFIG_CMD_I2C
	34	#define CONFIG_CMD_PING
	35	#define CONFIG_CMD_SF
	36	#define CONFIG_CMD_SPI
	37	#define CONFIG_CMD_TFTPPUT
	38	#define CONFIG_CMD_TIME
	39
	40	/* I2C */
	41	#define CONFIG_SYS_I2C
	42	#define CONFIG_SYS_I2C_MVTWSI
dd82242b	43	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
a4884831 SR	44	#define CONFIG_SYS_I2C_SLAVE 0x0
	45	#define CONFIG_SYS_I2C_SPEED 100000
	46
	47	/* SPI NOR flash default params, used by sf commands */
	48	#define CONFIG_SF_DEFAULT_SPEED 1000000
	49	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
a4884831 SR	50
	51	/* Environment in SPI NOR flash */
	52	#define CONFIG_ENV_IS_IN_SPI_FLASH
	53	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	54	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	55	#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
	56
	57	#define CONFIG_PHY_MARVELL /* there is a marvell phy */
cae9008f	58	#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
a4884831 SR	59	#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
	60	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
	61	#define CONFIG_RESET_PHY_R
	62
	63	#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
	64	#define CONFIG_SYS_ALT_MEMTEST
	65
	66	/*
	67	* mv-common.h should be defined after CMD configs since it used them
	68	* to enable certain macros
	69	*/
	70	#include "mv-common.h"
	71
e7778ec1 SR	72	/*
	73	* Memory layout while starting into the bin_hdr via the
	74	* BootROM:
	75	*
	76	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	77	* 0x4000.4030 bin_hdr start address
	78	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	79	* 0x4007.fffc BootROM stack top
	80	*
	81	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	82	* L2 cache thus cannot be used.
	83	*/
	84
	85	/* SPL */
	86	/* Defines for SPL */
	87	#define CONFIG_SPL_FRAMEWORK
	88	#define CONFIG_SPL_TEXT_BASE 0x40004030
	89	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	90
	91	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	92	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	93
6451223a SR	94	#ifdef CONFIG_SPL_BUILD
	95	#define CONFIG_SYS_MALLOC_SIMPLE
	96	#endif
e7778ec1 SR	97
	98	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	99	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	100
	101	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	102	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	103	#define CONFIG_SPL_SERIAL_SUPPORT
	104	#define CONFIG_SPL_I2C_SUPPORT
e7778ec1 SR	105
	106	/* SPL related SPI defines */
	107	#define CONFIG_SPL_SPI_SUPPORT
	108	#define CONFIG_SPL_SPI_FLASH_SUPPORT
	109	#define CONFIG_SPL_SPI_LOAD
	110	#define CONFIG_SPL_SPI_BUS 0
	111	#define CONFIG_SPL_SPI_CS 0
	112	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
	113
	114	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
ff9112df	115	#define CONFIG_SYS_MVEBU_DDR_AXP
e7778ec1 SR	116	#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
e7778ec1 SR	117
a4884831	118	#endif /* _CONFIG_DB_MV7846MP_GP_H */