projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| a4884831 SR |
2 | /* |
| 3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> | |
| a4884831 SR |
4 | */ |
| 5 | ||
| 6 | #ifndef _CONFIG_DB_MV7846MP_GP_H | |
| 7 | #define _CONFIG_DB_MV7846MP_GP_H | |
| 8 | ||
| 9 | /* | |
| 10 | * High Level Configuration Options (easy to change) | |
| 11 | */ | |
| a4884831 | 12 | |
| 2923c2d2 SR |
13 | /* |
| 14 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed | |
| 15 | * for DDR ECC byte filling in the SPL before loading the main | |
| 16 | * U-Boot into it. | |
| 17 | */ | |
| a4884831 SR |
18 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
| 19 | ||
| 20 | /* | |
| 21 | * Commands configuration | |
| 22 | */ | |
| a4884831 SR |
23 | |
| 24 | /* I2C */ | |
| 25 | #define CONFIG_SYS_I2C | |
| 26 | #define CONFIG_SYS_I2C_MVTWSI | |
| dd82242b | 27 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
| a4884831 SR |
28 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
| 29 | #define CONFIG_SYS_I2C_SPEED 100000 | |
| 30 | ||
| 31 | /* SPI NOR flash default params, used by sf commands */ | |
| a4884831 SR |
32 | |
| 33 | /* Environment in SPI NOR flash */ | |
| a4884831 | 34 | |
| a4884831 | 35 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
| a4884831 | 36 | |
| a4884831 SR |
37 | /* |
| 38 | * mv-common.h should be defined after CMD configs since it used them | |
| 39 | * to enable certain macros | |
| 40 | */ | |
| 41 | #include "mv-common.h" | |
| 42 | ||
| e7778ec1 SR |
43 | /* |
| 44 | * Memory layout while starting into the bin_hdr via the | |
| 45 | * BootROM: | |
| 46 | * | |
| 47 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) | |
| 48 | * 0x4000.4030 bin_hdr start address | |
| 49 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) | |
| 50 | * 0x4007.fffc BootROM stack top | |
| 51 | * | |
| 52 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in | |
| 53 | * L2 cache thus cannot be used. | |
| 54 | */ | |
| 55 | ||
| 56 | /* SPL */ | |
| 57 | /* Defines for SPL */ | |
| e7778ec1 SR |
58 | #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) |
| 59 | ||
| 60 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) | |
| 61 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) | |
| 62 | ||
| 6451223a SR |
63 | #ifdef CONFIG_SPL_BUILD |
| 64 | #define CONFIG_SYS_MALLOC_SIMPLE | |
| 65 | #endif | |
| e7778ec1 SR |
66 | |
| 67 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) | |
| 68 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) | |
| 69 | ||
| e7778ec1 | 70 | /* SPL related SPI defines */ |
| e7778ec1 SR |
71 | |
| 72 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ | |
| e7778ec1 | 73 | #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ |
| 698ffab2 | 74 | #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ |
| e7778ec1 | 75 | |
| a4884831 | 76 | #endif /* _CONFIG_DB_MV7846MP_GP_H */ |