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86ea5f93 | 1 | /* |
a99715b8 | 2 | * (C) Copyright 2006-2008 |
86ea5f93 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | ||
32 | #define CONFIG_MPC5200 | |
33 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
34 | #define CONFIG_MCC200 1 /* ... on MCC200 board */ | |
35 | ||
36 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ | |
37 | ||
38 | #define CONFIG_MISC_INIT_R | |
39 | ||
360b4103 WD |
40 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
41 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
86ea5f93 | 42 | |
31d82672 BB |
43 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
44 | ||
86ea5f93 WD |
45 | /* |
46 | * Serial console configuration | |
87791f3b WD |
47 | * |
48 | * To select console on the one of 8 external UARTs, | |
49 | * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, | |
50 | * or as 5, 6, 7, or 8 for the second Quad UART. | |
463764c8 | 51 | * COM11, COM12, COM13, COM14 are located on the second Quad UART. |
87791f3b WD |
52 | * |
53 | * CONFIG_PSC_CONSOLE must be undefined in this case. | |
54 | */ | |
ed1cf845 WD |
55 | #if !defined(CONFIG_PRS200) |
56 | /* MCC200 configuration: */ | |
463764c8 WD |
57 | #ifdef CONFIG_CONSOLE_COM12 |
58 | #define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ | |
59 | #else | |
60 | #define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ | |
61 | #endif | |
ed1cf845 WD |
62 | #else |
63 | /* PRS200 configuration: */ | |
64 | #undef CONFIG_QUART_CONSOLE | |
65 | #endif /* CONFIG_PRS200 */ | |
87791f3b WD |
66 | /* |
67 | * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 | |
68 | * and undefine CONFIG_QUART_CONSOLE. | |
86ea5f93 | 69 | */ |
ed1cf845 WD |
70 | #if !defined(CONFIG_PRS200) |
71 | /* MCC200 configuration: */ | |
0fd30252 WD |
72 | #define CONFIG_SERIAL_MULTI 1 |
73 | #define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ | |
74 | #define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ | |
ed1cf845 WD |
75 | #else |
76 | /* PRS200 configuration: */ | |
77 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
78 | #endif | |
0fd30252 WD |
79 | #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \ |
80 | !defined(CONFIG_SERIAL_MULTI) | |
87791f3b WD |
81 | #error "Select only one console device!" |
82 | #endif | |
86ea5f93 WD |
83 | #define CONFIG_BAUDRATE 115200 |
84 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
85 | ||
86ea5f93 | 86 | #define CONFIG_MII 1 |
86ea5f93 | 87 | |
86ea5f93 WD |
88 | #define CONFIG_DOS_PARTITION |
89 | ||
90 | /* USB */ | |
86ea5f93 | 91 | #define CONFIG_USB_OHCI |
86ea5f93 | 92 | #define CONFIG_USB_STORAGE |
cdb97a66 AS |
93 | /* automatic software updates (see board/mcc200/auto_update.c) */ |
94 | #define CONFIG_AUTO_UPDATE 1 | |
86ea5f93 | 95 | |
5dc11a51 | 96 | |
7f5c0157 JL |
97 | /* |
98 | * BOOTP options | |
99 | */ | |
100 | #define CONFIG_BOOTP_BOOTFILESIZE | |
101 | #define CONFIG_BOOTP_BOOTPATH | |
102 | #define CONFIG_BOOTP_GATEWAY | |
103 | #define CONFIG_BOOTP_HOSTNAME | |
104 | ||
105 | ||
86ea5f93 | 106 | /* |
5dc11a51 | 107 | * Command line configuration. |
86ea5f93 | 108 | */ |
5dc11a51 JL |
109 | #include <config_cmd_default.h> |
110 | ||
111 | #define CONFIG_CMD_BEDBUG | |
112 | #define CONFIG_CMD_FAT | |
113 | #define CONFIG_CMD_I2C | |
114 | #define CONFIG_CMD_USB | |
86ea5f93 | 115 | |
a4d2636f WD |
116 | #undef CONFIG_CMD_NET |
117 | ||
86ea5f93 WD |
118 | |
119 | /* | |
120 | * Autobooting | |
121 | */ | |
a4d2636f | 122 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
86ea5f93 WD |
123 | |
124 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 125 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
86ea5f93 WD |
126 | "echo" |
127 | ||
128 | #undef CONFIG_BOOTARGS | |
129 | ||
3b0ff842 WD |
130 | #define XMK_STR(x) #x |
131 | #define MK_STR(x) XMK_STR(x) | |
ed1cf845 WD |
132 | |
133 | #ifdef CONFIG_PRS200 | |
3b0ff842 WD |
134 | # define CFG__BOARDNAME "prs200" |
135 | # define CFG__LINUX_CONSOLE "ttyS0" | |
ed1cf845 | 136 | #else |
3b0ff842 | 137 | # define CFG__BOARDNAME "mcc200" |
a4d2636f | 138 | # define CFG__LINUX_CONSOLE "ttyEU5" |
ed1cf845 WD |
139 | #endif |
140 | ||
a4d2636f WD |
141 | /* Network */ |
142 | #define CONFIG_ETHADDR 00:17:17:ff:00:00 | |
143 | #define CONFIG_IPADDR 10.76.9.29 | |
144 | #define CONFIG_SERVERIP 10.76.9.1 | |
145 | ||
146 | #include <version.h> /* For U-Boot version */ | |
147 | ||
ed1cf845 | 148 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
a4d2636f | 149 | "ubootver=" U_BOOT_VERSION "\0" \ |
86ea5f93 | 150 | "netdev=eth0\0" \ |
ed1cf845 | 151 | "hostname=" CFG__BOARDNAME "\0" \ |
86ea5f93 WD |
152 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
153 | "nfsroot=${serverip}:${rootpath}\0" \ | |
a4d2636f WD |
154 | "ramargs=setenv bootargs root=/dev/mtdblock2 " \ |
155 | "rootfstype=cramfs\0" \ | |
86ea5f93 WD |
156 | "addip=setenv bootargs ${bootargs} " \ |
157 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
158 | ":${hostname}:${netdev}:off panic=1\0" \ | |
113f64e0 | 159 | "addcons=setenv bootargs ${bootargs} " \ |
a99715b8 DZ |
160 | "console=${console},${baudrate} " \ |
161 | "ubootver=${ubootver} board=${board}\0" \ | |
ed1cf845 | 162 | "flash_nfs=run nfsargs addip addcons;" \ |
86ea5f93 | 163 | "bootm ${kernel_addr}\0" \ |
ed1cf845 | 164 | "flash_self=run ramargs addip addcons;" \ |
86ea5f93 | 165 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
ed1cf845 WD |
166 | "net_nfs=tftp 200000 ${bootfile};" \ |
167 | "run nfsargs addip addcons;bootm\0" \ | |
21a9cc02 | 168 | "console=" CFG__LINUX_CONSOLE "\0" \ |
82f2e33a | 169 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
ed1cf845 WD |
170 | "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ |
171 | "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ | |
172 | "text_base=" MK_STR(TEXT_BASE) "\0" \ | |
a4d2636f | 173 | "kernel_addr=0xFC0C0000\0" \ |
ed1cf845 WD |
174 | "update=protect off ${text_base} +${filesize};" \ |
175 | "era ${text_base} +${filesize};" \ | |
176 | "cp.b 200000 ${text_base} ${filesize}\0" \ | |
58ad4978 | 177 | "unlock=yes\0" \ |
86ea5f93 | 178 | "" |
ed1cf845 WD |
179 | #undef MK_STR |
180 | #undef XMK_STR | |
86ea5f93 WD |
181 | |
182 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
183 | ||
82f2e33a WD |
184 | #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ |
185 | #define CFG_PROMPT_HUSH_PS2 "> " | |
186 | ||
86ea5f93 WD |
187 | /* |
188 | * IPB Bus clocking configuration. | |
189 | */ | |
c99512d6 | 190 | #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
86ea5f93 | 191 | |
86ea5f93 WD |
192 | /* |
193 | * I2C configuration | |
194 | */ | |
195 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
cdb97a66 | 196 | #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
86ea5f93 WD |
197 | |
198 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
199 | #define CFG_I2C_SLAVE 0x7F | |
200 | ||
86ea5f93 WD |
201 | /* |
202 | * Flash configuration (8,16 or 32 MB) | |
203 | * TEXT base always at 0xFFF00000 | |
204 | * ENV_ADDR always at 0xFFF40000 | |
58ad4978 | 205 | * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) |
360b4103 WD |
206 | * 0xFE000000 for 32 MB |
207 | * 0xFF000000 for 16 MB | |
208 | * 0xFF800000 for 8 MB | |
86ea5f93 | 209 | */ |
58ad4978 SR |
210 | #define CFG_FLASH_BASE 0xfc000000 |
211 | #define CFG_FLASH_SIZE 0x04000000 | |
86ea5f93 | 212 | |
58ad4978 | 213 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 214 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
86ea5f93 | 215 | |
58ad4978 | 216 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
86ea5f93 | 217 | |
58ad4978 SR |
218 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
219 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
86ea5f93 | 220 | |
58ad4978 SR |
221 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
222 | #define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ | |
86ea5f93 | 223 | |
58ad4978 SR |
224 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
225 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
86ea5f93 | 226 | |
58ad4978 SR |
227 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
228 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
229 | ||
5a1aceb0 | 230 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
58ad4978 | 231 | |
0e8d1586 JCPV |
232 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
233 | #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) | |
234 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
58ad4978 SR |
235 | |
236 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
237 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
238 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
58ad4978 SR |
239 | |
240 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
86ea5f93 | 241 | |
f149d864 WD |
242 | #if TEXT_BASE == CFG_FLASH_BASE |
243 | #define CFG_LOWBOOT 1 | |
244 | #endif | |
245 | ||
86ea5f93 WD |
246 | /* |
247 | * Memory map | |
248 | */ | |
249 | #define CFG_MBAR 0xf0000000 | |
250 | #define CFG_SDRAM_BASE 0x00000000 | |
251 | #define CFG_DEFAULT_MBAR 0x80000000 | |
252 | ||
253 | /* Use SRAM until RAM will be available */ | |
254 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
255 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
256 | ||
257 | ||
258 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
259 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
260 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
261 | ||
360b4103 | 262 | #define CFG_MONITOR_BASE TEXT_BASE |
86ea5f93 WD |
263 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
264 | # define CFG_RAMBOOT 1 | |
265 | #endif | |
266 | ||
267 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
58ad4978 | 268 | #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
86ea5f93 WD |
269 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
270 | ||
271 | /* | |
272 | * Ethernet configuration | |
273 | */ | |
a4d2636f | 274 | /*#define CONFIG_MPC5xxx_FEC 1*/ |
86ea5f93 WD |
275 | /* |
276 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
277 | */ | |
278 | /* #define CONFIG_FEC_10MBIT 1 */ | |
58ad4978 | 279 | #define CONFIG_PHY_ADDR 1 |
86ea5f93 | 280 | |
e8143e72 WD |
281 | /* |
282 | * LCD Splash Screen | |
283 | */ | |
360b4103 | 284 | #if !defined(CONFIG_PRS200) |
e8143e72 | 285 | #define CONFIG_LCD 1 |
638dd145 | 286 | #define CONFIG_PROGRESSBAR 1 |
360b4103 WD |
287 | #endif |
288 | ||
e8143e72 WD |
289 | #if defined(CONFIG_LCD) |
290 | #define CONFIG_SPLASH_SCREEN 1 | |
291 | #define CFG_CONSOLE_IS_IN_ENV 1 | |
360b4103 | 292 | #define LCD_BPP LCD_MONOCHROME |
e8143e72 WD |
293 | #endif |
294 | ||
86ea5f93 WD |
295 | /* |
296 | * GPIO configuration | |
297 | */ | |
bfc81252 WD |
298 | /* 0x10000004 = 32MB SDRAM */ |
299 | /* 0x90000004 = 64MB SDRAM */ | |
e8143e72 WD |
300 | #if defined(CONFIG_LCD) |
301 | /* set PSC2 in UART mode */ | |
302 | #define CFG_GPS_PORT_CONFIG 0x00000044 | |
303 | #else | |
5725f94a | 304 | #define CFG_GPS_PORT_CONFIG 0x00000004 |
e8143e72 | 305 | #endif |
86ea5f93 WD |
306 | |
307 | /* | |
308 | * Miscellaneous configurable options | |
309 | */ | |
360b4103 WD |
310 | #define CFG_LONGHELP /* undef to save memory */ |
311 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
5dc11a51 | 312 | #if defined(CONFIG_CMD_KGDB) |
360b4103 | 313 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
86ea5f93 | 314 | #else |
360b4103 | 315 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
86ea5f93 | 316 | #endif |
360b4103 | 317 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
86ea5f93 WD |
318 | #define CFG_MAXARGS 16 /* max number of command args */ |
319 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
320 | ||
360b4103 | 321 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
86ea5f93 WD |
322 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
323 | ||
324 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
325 | ||
326 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
327 | ||
5dc11a51 JL |
328 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
329 | #if defined(CONFIG_CMD_KGDB) | |
330 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
331 | #endif | |
332 | ||
86ea5f93 WD |
333 | /* |
334 | * Various low-level settings | |
335 | */ | |
86ea5f93 WD |
336 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
337 | #define CFG_HID0_FINAL HID0_ICE | |
86ea5f93 | 338 | |
86ea5f93 WD |
339 | #define CFG_BOOTCS_START CFG_FLASH_BASE |
340 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
341 | #define CFG_BOOTCS_CFG 0x0004fb00 | |
342 | #define CFG_CS0_START CFG_FLASH_BASE | |
343 | #define CFG_CS0_SIZE CFG_FLASH_SIZE | |
86ea5f93 | 344 | |
05d8dce9 WD |
345 | /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ |
346 | #define CFG_CS2_START 0x80000000 | |
347 | #define CFG_CS2_SIZE 0x00001000 | |
b81a4630 | 348 | #define CFG_CS2_CFG 0x1d300 |
05d8dce9 | 349 | |
a874c8c6 WD |
350 | /* Second Quad UART @0x80010000 */ |
351 | #define CFG_CS1_START 0x80010000 | |
352 | #define CFG_CS1_SIZE 0x00001000 | |
353 | #define CFG_CS1_CFG 0x1d300 | |
354 | ||
a4d2636f WD |
355 | /* Leica - build revision resistors */ |
356 | /* | |
357 | #define CFG_CS3_START 0x80020000 | |
358 | #define CFG_CS3_SIZE 0x00000004 | |
359 | #define CFG_CS3_CFG 0x1d300 | |
360 | */ | |
361 | ||
87791f3b WD |
362 | /* |
363 | * Select one of quarts as a default | |
364 | * console. If undefined - PSC console | |
365 | * wil be default | |
366 | */ | |
86ea5f93 WD |
367 | #define CFG_CS_BURST 0x00000000 |
368 | #define CFG_CS_DEADCYCLE 0x33333333 | |
369 | ||
370 | #define CFG_RESET_ADDRESS 0xff000000 | |
371 | ||
87791f3b WD |
372 | /* |
373 | * QUART Expanders support | |
374 | */ | |
375 | #if defined(CONFIG_QUART_CONSOLE) | |
376 | /* | |
377 | * We'll use NS16550 chip routines, | |
378 | */ | |
379 | #define CFG_NS16550 1 | |
380 | #define CFG_NS16550_SERIAL 1 | |
381 | #define CONFIG_CONS_INDEX 1 | |
382 | /* | |
383 | * To achieve necessary offset on SC16C554 | |
384 | * A0-A2 (register select) pins with NS16550 | |
385 | * functions (in struct NS16550), REG_SIZE | |
386 | * should be 4, because A0-A2 pins are connected | |
387 | * to DA2-DA4 address bus lines. | |
388 | */ | |
389 | #define CFG_NS16550_REG_SIZE 4 | |
390 | /* | |
391 | * LocalPlus Bus already inited in cpu_init_f(), | |
392 | * so can work with QUART's chip selects. | |
393 | * One of four SC16C554 UARTs is selected with | |
394 | * A3-A4 (DA5-DA6) lines. | |
395 | */ | |
ed1cf845 | 396 | #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) |
87791f3b WD |
397 | #define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) |
398 | #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) | |
399 | #define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) | |
400 | #elif | |
401 | #error "Wrong QUART expander number." | |
402 | #endif | |
403 | ||
404 | /* | |
405 | * SC16C554 chip's external crystal oscillator frequency | |
406 | * is 7.3728 MHz | |
407 | */ | |
408 | #define CFG_NS16550_CLK 7372800 | |
409 | #endif /* CONFIG_QUART_CONSOLE */ | |
86ea5f93 WD |
410 | /*----------------------------------------------------------------------- |
411 | * USB stuff | |
412 | *----------------------------------------------------------------------- | |
413 | */ | |
414 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
415 | #define CONFIG_USB_CONFIG 0x00005000 | |
416 | ||
a4d2636f WD |
417 | #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
418 | #define CONFIG_AUTOBOOT_STOP_STR "432" | |
419 | #define CONFIG_SILENT_CONSOLE 1 | |
420 | ||
86ea5f93 | 421 | #endif /* __CONFIG_H */ |