[people/ms/u-boot.git] / include / configs / mcu25.h

/*
 *(C) Copyright 2005-2007 Netstal Maschinen AG
 *    Niklaus Giger (Niklaus.Giger@netstal.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * mcu25.h - configuration for MCU25 board (similar to hcu4.h)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_MCU25		1		/* Board is MCU25	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_405GP 1
#define CONFIG_4xx   1
#define CONFIG_HOSTNAME		mcu25

/*
 * Include common defines/options for all boards produced by Netstal Maschinen
 */
#include "netstal-common.h"

#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN		(320 * 1024) /* Reserve 320 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc() */


#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
#define CONFIG_SYS_FLASH_BASE		0xfff80000	/* start of FLASH	*/
#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE

/* ... with on-chip memory here (4KBytes) */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF4000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x00001000
/* Do not set up locked dcache as init ram. */
#undef CONFIG_SYS_INIT_DCACHE_CS

/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
#define CONFIG_SYS_TEMP_STACK_OCM	1

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* OCM		*/
#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE
#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
/*
 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD	    691200

/* Size (bytes) of interrupt driven serial port buffer.
 * Set to 0 to use polling instead of interrupts.
 * Setting to 0 will also disable RTS/CTS handshaking.
 */
#undef CONFIG_SERIAL_SOFTWARE_FIFO

/* Set console baudrate to 9600 */
#define CONFIG_BAUDRATE		9600

/*-----------------------------------------------------------------------
 * Flash
 *----------------------------------------------------------------------*/

/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* board provides its own flash_init code */
#define CONFIG_FLASH_CFI_LEGACY		1
#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_8BIT
#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1

/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip */

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/

#undef	CONFIG_ENV_IS_IN_NVRAM
#define CONFIG_ENV_IS_IN_FLASH
#undef  CONFIG_ENV_IS_NOWHERE

#ifdef  CONFIG_ENV_IS_IN_EEPROM
/* Put the environment after the SDRAM configuration */
#define PROM_SIZE	2048
#define CONFIG_ENV_OFFSET	 512
#define CONFIG_ENV_SIZE	(PROM_SIZE-CONFIG_ENV_OFFSET)
#endif

#ifdef CONFIG_ENV_IS_IN_FLASH
/* Put the environment in Flash */
#define CONFIG_ENV_SECT_SIZE	0x10000 /* size of one complete sector */
#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		8*1024	/* 8 KB Environment Sector */

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
 * the first internal I2C controller of the PPC440EPx
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_SPD_BUS_NUM		0

/* Setup some board specific values for the default environment variables */
#define CONFIG_IPADDR		172.25.1.25

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_NETSTAL_DEF_ENV						\
	CONFIG_NETSTAL_DEF_ENV_POWERPC					\
	""

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM

/* SPD EEPROM (sdram speed config) disabled */
#define CONFIG_SPD_EEPROM          1
#define SPD_EEPROM_ADDRESS      0x50

/* POST support */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
				 CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_UART	   | \
				 CONFIG_SYS_POST_I2C	   | \
				 CONFIG_SYS_POST_CACHE	   | \
				 CONFIG_SYS_POST_ETHER	   | \
				 CONFIG_SYS_POST_SPR)

#define CONFIG_SYS_POST_UART_TABLE	{UART0_BASE}
#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#undef  CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/


#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

#define CONFIG_SYS_EBC_CFG            0x98400000

/* Memory Bank 0 (Flash Bank 0) initialization	*/
#define CONFIG_SYS_EBC_PB0AP		0x02005400
#define CONFIG_SYS_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/

#define CONFIG_SYS_EBC_PB1AP		0x03041200
#define CONFIG_SYS_EBC_PB1CR		0x7009A000  /* BAS=,BS=MB,BU=R/W,BW=bit	*/

#define CONFIG_SYS_EBC_PB2AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CONFIG_SYS_EBC_PB2CR		0x7A09A000u

#define CONFIG_SYS_EBC_PB3AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CONFIG_SYS_EBC_PB3CR		0x7B09A000u

#define CONFIG_SYS_EBC_PB4AP		0x01845200u  /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CONFIG_SYS_EBC_PB4CR		0x7C09A000u

#define CONFIG_SYS_EBC_PB5AP		0x00800200u
#define CONFIG_SYS_EBC_PB5CR		0x7D81A000u

#define CONFIG_SYS_EBC_PB6AP		0x01040200u
#define CONFIG_SYS_EBC_PB6CR		0x7D91A000u

#define CONFIG_SYS_GPIO0_OR		0x087FFFFF  /* GPIO value */
#define CONFIG_SYS_GPIO0_TCR		0x7FFF8000  /* GPIO value */
#define CONFIG_SYS_GPIO0_ODR		0xFFFF0000  /* GPIO value */
/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/* Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/


/* Configuration Port location */
#define CONFIG_PORT_ADDR	0xF0000500

#define CONFIG_SYS_HUSH_PARSER                 /* use "hush" command parser    */
#ifdef  CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
75a66dcd NG	1	/*
	2	*(C) Copyright 2005-2007 Netstal Maschinen AG
	3	* Niklaus Giger (Niklaus.Giger@netstal.com)
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/************************************************************************
	25	* mcu25.h - configuration for MCU25 board (similar to hcu4.h)
	26	***********************************************************************/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*-----------------------------------------------------------------------
	32	* High Level Configuration Options
	33	----------------------------------------------------------------------/
	34	#define CONFIG_MCU25 1 /* Board is MCU25 */
	35	#define CONFIG_4xx 1 /* ... PPC4xx family */
	36	#define CONFIG_405GP 1
	37	#define CONFIG_4xx 1
c11da194 NG	38	#define CONFIG_HOSTNAME mcu25
	39
	40	/*
	41	* Include common defines/options for all boards produced by Netstal Maschinen
	42	*/
	43	#include "netstal-common.h"
75a66dcd NG	44
	45	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	46
	47	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	48	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	49
	50	/*-----------------------------------------------------------------------
	51	* Base addresses -- Note these are effective addresses where the
	52	* actual resources get mapped (not physical addresses)
	53	----------------------------------------------------------------------/
6d0f6bcf JCPV	54	#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
6d0f6bcf JCPV	55	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
75a66dcd NG	56
75a66dcd NG	57
6d0f6bcf JCPV	58	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	59	#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
	60	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
75a66dcd NG	61
75a66dcd NG	62	/* ... with on-chip memory here (4KBytes) */
6d0f6bcf JCPV	63	#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
6d0f6bcf JCPV	64	#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
75a66dcd	65	/* Do not set up locked dcache as init ram. */
6d0f6bcf	66	#undef CONFIG_SYS_INIT_DCACHE_CS
75a66dcd NG	67
75a66dcd NG	68	/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
6d0f6bcf	69	#define CONFIG_SYS_TEMP_STACK_OCM 1
75a66dcd	70
6d0f6bcf JCPV	71	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* OCM */
	72	#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
	73	#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
	74	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	75	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
75a66dcd NG	76
	77	/*-----------------------------------------------------------------------
	78	* Serial Port
	79	----------------------------------------------------------------------/
	80	/*
6d0f6bcf JCPV	81	* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	82	* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
	83	* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
75a66dcd NG	84	* The Linux BASE_BAUD define should match this configuration.
75a66dcd NG	85	* baseBaud = cpuClock/(uartDivisor*16)
6d0f6bcf	86	* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
75a66dcd NG	87	* set Linux BASE_BAUD to 403200.
75a66dcd NG	88	*/
75a66dcd	89	/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
6d0f6bcf JCPV	90	#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
6d0f6bcf JCPV	91	#define CONFIG_SYS_BASE_BAUD 691200
75a66dcd NG	92
	93	/* Size (bytes) of interrupt driven serial port buffer.
	94	* Set to 0 to use polling instead of interrupts.
	95	* Setting to 0 will also disable RTS/CTS handshaking.
	96	*/
	97	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	98
	99	/* Set console baudrate to 9600 */
	100	#define CONFIG_BAUDRATE 9600
	101
75a66dcd NG	102	/*-----------------------------------------------------------------------
	103	* Flash
	104	----------------------------------------------------------------------/
	105
	106	/* Use common CFI driver */
6d0f6bcf	107	#define CONFIG_SYS_FLASH_CFI
00b1883a	108	#define CONFIG_FLASH_CFI_DRIVER
75a66dcd NG	109	/* board provides its own flash_init code */
75a66dcd NG	110	#define CONFIG_FLASH_CFI_LEGACY 1
6d0f6bcf JCPV	111	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
6d0f6bcf JCPV	112	#define CONFIG_SYS_FLASH_LEGACY_512Kx8 1
75a66dcd NG	113
75a66dcd NG	114	/* print 'E' for empty sector on flinfo */
6d0f6bcf	115	#define CONFIG_SYS_FLASH_EMPTY_INFO
75a66dcd	116
6d0f6bcf JCPV	117	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	118	#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
75a66dcd NG	119
	120	/*-----------------------------------------------------------------------
	121	* Environment
	122	----------------------------------------------------------------------/
	123
9314cee6	124	#undef CONFIG_ENV_IS_IN_NVRAM
5a1aceb0	125	#define CONFIG_ENV_IS_IN_FLASH
93f6d725	126	#undef CONFIG_ENV_IS_NOWHERE
75a66dcd	127
bb1f8b4f	128	#ifdef CONFIG_ENV_IS_IN_EEPROM
75a66dcd	129	/* Put the environment after the SDRAM configuration */
53677ef1	130	#define PROM_SIZE 2048
0e8d1586 JCPV	131	#define CONFIG_ENV_OFFSET 512
0e8d1586 JCPV	132	#define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET)
75a66dcd NG	133	#endif
75a66dcd NG	134
5a1aceb0	135	#ifdef CONFIG_ENV_IS_IN_FLASH
75a66dcd	136	/* Put the environment in Flash */
0e8d1586	137	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
6d0f6bcf	138	#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586	139	#define CONFIG_ENV_SIZE 81024 / 8 KB Environment Sector */
75a66dcd NG	140
75a66dcd NG	141	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	142	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	143	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
75a66dcd NG	144	#endif
	145
	146	/*-----------------------------------------------------------------------
	147	* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
	148	* the first internal I2C controller of the PPC440EPx
	149	----------------------------------------------------------------------/
6d0f6bcf	150	#define CONFIG_SYS_SPD_BUS_NUM 0
75a66dcd	151
75a66dcd	152	/* Setup some board specific values for the default environment variables */
c11da194	153	#define CONFIG_IPADDR 172.25.1.25
75a66dcd	154
c11da194 NG	155	#define CONFIG_EXTRA_ENV_SETTINGS \
	156	CONFIG_NETSTAL_DEF_ENV \
	157	CONFIG_NETSTAL_DEF_ENV_POWERPC \
	158	""
75a66dcd NG	159
	160	/*
	161	* BOOTP options
	162	*/
	163	#define CONFIG_BOOTP_BOOTFILESIZE
	164	#define CONFIG_BOOTP_BOOTPATH
	165	#define CONFIG_BOOTP_GATEWAY
	166	#define CONFIG_BOOTP_HOSTNAME
	167
	168	/*
	169	* Command line configuration.
	170	*/
	171	#include <config_cmd_default.h>
	172
	173	#define CONFIG_CMD_ASKENV
	174	#define CONFIG_CMD_CACHE
	175	#define CONFIG_CMD_DHCP
	176	#define CONFIG_CMD_DIAG
	177	#define CONFIG_CMD_EEPROM
	178	#define CONFIG_CMD_ELF
	179	#define CONFIG_CMD_FLASH
	180	#define CONFIG_CMD_I2C
	181	#define CONFIG_CMD_IMMAP
	182	#define CONFIG_CMD_IRQ
	183	#define CONFIG_CMD_MII
	184	#define CONFIG_CMD_NET
	185	#define CONFIG_CMD_PING
	186	#define CONFIG_CMD_REGINFO
	187	#define CONFIG_CMD_SDRAM
	188
	189	/* SPD EEPROM (sdram speed config) disabled */
	190	#define CONFIG_SPD_EEPROM 1
	191	#define SPD_EEPROM_ADDRESS 0x50
	192
	193	/* POST support */
6d0f6bcf JCPV	194	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	195	CONFIG_SYS_POST_CPU \| \
	196	CONFIG_SYS_POST_UART \| \
	197	CONFIG_SYS_POST_I2C \| \
	198	CONFIG_SYS_POST_CACHE \| \
	199	CONFIG_SYS_POST_ETHER \| \
	200	CONFIG_SYS_POST_SPR)
	201
	202	#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
	203	#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
75a66dcd	204	#undef CONFIG_LOGBUFFER
6d0f6bcf JCPV	205	#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
6d0f6bcf JCPV	206	#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
75a66dcd NG	207
	208	/*-----------------------------------------------------------------------
	209	* Miscellaneous configurable options
	210	----------------------------------------------------------------------/
6d0f6bcf JCPV	211	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	212	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
75a66dcd	213	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	214	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
75a66dcd	215	#else
6d0f6bcf	216	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
75a66dcd	217	#endif
6d0f6bcf JCPV	218	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	219	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	220	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
75a66dcd	221
6d0f6bcf JCPV	222	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	223	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
75a66dcd NG	224
75a66dcd NG	225
6d0f6bcf	226	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
75a66dcd NG	227
	228	/*-----------------------------------------------------------------------
	229	* External Bus Controller (EBC) Setup
	230	*/
	231
6d0f6bcf	232	#define CONFIG_SYS_EBC_CFG 0x98400000
75a66dcd NG	233
75a66dcd NG	234	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	235	#define CONFIG_SYS_EBC_PB0AP 0x02005400
6d0f6bcf JCPV	236	#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit*/
75a66dcd	237
6d0f6bcf JCPV	238	#define CONFIG_SYS_EBC_PB1AP 0x03041200
6d0f6bcf JCPV	239	#define CONFIG_SYS_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
75a66dcd	240
6d0f6bcf JCPV	241	#define CONFIG_SYS_EBC_PB2AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
6d0f6bcf JCPV	242	#define CONFIG_SYS_EBC_PB2CR 0x7A09A000u
75a66dcd	243
6d0f6bcf JCPV	244	#define CONFIG_SYS_EBC_PB3AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
6d0f6bcf JCPV	245	#define CONFIG_SYS_EBC_PB3CR 0x7B09A000u
75a66dcd	246
6d0f6bcf JCPV	247	#define CONFIG_SYS_EBC_PB4AP 0x01845200u /* BAS=,BS=MB,BU=R/W,BW=bit */
6d0f6bcf JCPV	248	#define CONFIG_SYS_EBC_PB4CR 0x7C09A000u
75a66dcd	249
6d0f6bcf JCPV	250	#define CONFIG_SYS_EBC_PB5AP 0x00800200u
6d0f6bcf JCPV	251	#define CONFIG_SYS_EBC_PB5CR 0x7D81A000u
75a66dcd	252
6d0f6bcf JCPV	253	#define CONFIG_SYS_EBC_PB6AP 0x01040200u
6d0f6bcf JCPV	254	#define CONFIG_SYS_EBC_PB6CR 0x7D91A000u
75a66dcd	255
6d0f6bcf JCPV	256	#define CONFIG_SYS_GPIO0_OR 0x087FFFFF /* GPIO value */
	257	#define CONFIG_SYS_GPIO0_TCR 0x7FFF8000 /* GPIO value */
	258	#define CONFIG_SYS_GPIO0_ODR 0xFFFF0000 /* GPIO value */
75a66dcd NG	259	/*
	260	* For booting Linux, the board info and command line data
	261	* have to be in the first 8 MB of memory, since this is
	262	* the maximum mapped by the Linux kernel during initialization.
	263	*/
6d0f6bcf	264	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
75a66dcd NG	265
	266	/* Init Memory Controller:
	267	*
	268	* BR0/1 and OR0/1 (FLASH)
	269	*/
	270
6d0f6bcf	271	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
75a66dcd NG	272	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	273
	274
	275	/* Configuration Port location */
	276	#define CONFIG_PORT_ADDR 0xF0000500
	277
6d0f6bcf JCPV	278	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	279	#ifdef CONFIG_SYS_HUSH_PARSER
	280	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
75a66dcd NG	281	#endif
	282
	283	#if defined(CONFIG_CMD_KGDB)
	284	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	285	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	286	#endif
	287
75a66dcd	288	#endif /* __CONFIG_H */