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4ab779cb IY |
1 | /* |
2 | * Copyright (C) 2011 Ilya Yanok, Emcraft Systems | |
3 | * | |
4 | * Based on omap3_evm_config.h | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc. | |
19 | */ | |
20 | ||
21 | #ifndef __CONFIG_H | |
22 | #define __CONFIG_H | |
23 | ||
24 | /* | |
25 | * High Level Configuration Options | |
26 | */ | |
27 | #define CONFIG_OMAP /* in a TI OMAP core */ | |
28 | #define CONFIG_OMAP34XX /* which is a 34XX */ | |
29 | #define CONFIG_OMAP3_MCX /* working with mcx */ | |
308252ad | 30 | #define CONFIG_OMAP_GPIO |
4ab779cb IY |
31 | |
32 | #define MACH_TYPE_MCX 3656 | |
33 | #define CONFIG_MACH_TYPE MACH_TYPE_MCX | |
3ae6abb6 | 34 | #define CONFIG_BOARD_LATE_INIT |
4ab779cb IY |
35 | |
36 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
37 | ||
38 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ | |
39 | ||
40 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
41 | #include <asm/arch/omap3.h> | |
42 | ||
43 | #define CONFIG_OF_LIBFDT | |
44 | #define CONFIG_FIT | |
45 | ||
46 | /* | |
47 | * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader | |
48 | * and older u-boot.bin with the new U-Boot SPL. | |
49 | */ | |
50 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
51 | ||
52 | /* | |
53 | * Display CPU and Board information | |
54 | */ | |
55 | #define CONFIG_DISPLAY_CPUINFO | |
56 | #define CONFIG_DISPLAY_BOARDINFO | |
57 | ||
58 | /* Clock Defines */ | |
59 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
60 | #define V_SCLK (V_OSCK >> 1) | |
61 | ||
62 | #define CONFIG_MISC_INIT_R | |
63 | ||
64 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
65 | #define CONFIG_SETUP_MEMORY_TAGS | |
66 | #define CONFIG_INITRD_TAG | |
67 | #define CONFIG_REVISION_TAG | |
68 | ||
69 | /* | |
70 | * Size of malloc() pool | |
71 | */ | |
72 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ | |
73 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) | |
74 | /* | |
75 | * DDR related | |
76 | */ | |
77 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) | |
78 | ||
79 | /* | |
80 | * Hardware drivers | |
81 | */ | |
82 | ||
83 | /* | |
84 | * NS16550 Configuration | |
85 | */ | |
86 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
87 | ||
88 | #define CONFIG_SYS_NS16550 | |
89 | #define CONFIG_SYS_NS16550_SERIAL | |
90 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
91 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
92 | ||
93 | /* | |
94 | * select serial console configuration | |
95 | */ | |
96 | #define CONFIG_CONS_INDEX 3 | |
97 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
98 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
99 | ||
100 | /* allow to overwrite serial and ethaddr */ | |
101 | #define CONFIG_ENV_OVERWRITE | |
102 | #define CONFIG_BAUDRATE 115200 | |
103 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
104 | 115200} | |
105 | #define CONFIG_MMC | |
106 | #define CONFIG_OMAP_HSMMC | |
107 | #define CONFIG_GENERIC_MMC | |
108 | #define CONFIG_DOS_PARTITION | |
109 | ||
110 | /* EHCI */ | |
111 | #define CONFIG_USB_STORAGE | |
112 | #define CONFIG_OMAP3_GPIO_5 | |
113 | #define CONFIG_USB_EHCI | |
114 | #define CONFIG_USB_EHCI_OMAP | |
115 | #define CONFIG_USB_ULPI | |
116 | #define CONFIG_USB_ULPI_VIEWPORT_OMAP | |
8c735b99 | 117 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 |
4ab779cb IY |
118 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 |
119 | ||
120 | /* commands to include */ | |
121 | #include <config_cmd_default.h> | |
122 | ||
123 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
124 | #define CONFIG_CMD_FAT /* FAT support */ | |
125 | #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ | |
126 | ||
127 | #define CONFIG_CMD_DATE | |
128 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
129 | #define CONFIG_CMD_MMC /* MMC support */ | |
130 | #define CONFIG_CMD_FAT /* FAT support */ | |
131 | #define CONFIG_CMD_USB | |
132 | #define CONFIG_CMD_NAND /* NAND support */ | |
133 | #define CONFIG_CMD_DHCP | |
134 | #define CONFIG_CMD_PING | |
135 | #define CONFIG_CMD_CACHE | |
136 | #define CONFIG_CMD_UBI | |
137 | #define CONFIG_CMD_UBIFS | |
138 | #define CONFIG_RBTREE | |
139 | #define CONFIG_LZO | |
140 | #define CONFIG_MTD_PARTITIONS | |
141 | #define CONFIG_MTD_DEVICE | |
142 | #define CONFIG_CMD_MTDPARTS | |
3ae6abb6 | 143 | #define CONFIG_CMD_GPIO |
4ab779cb IY |
144 | |
145 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
146 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
147 | #undef CONFIG_CMD_IMI /* iminfo */ | |
148 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
149 | ||
150 | #define CONFIG_SYS_NO_FLASH | |
151 | #define CONFIG_HARD_I2C | |
152 | #define CONFIG_SYS_I2C_SPEED 100000 | |
153 | #define CONFIG_SYS_I2C_SLAVE 1 | |
4ab779cb IY |
154 | #define CONFIG_DRIVER_OMAP34XX_I2C |
155 | ||
156 | /* RTC */ | |
157 | #define CONFIG_RTC_DS1337 | |
158 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
159 | ||
160 | #define CONFIG_CMD_NET | |
161 | #define CONFIG_CMD_MII | |
162 | #define CONFIG_CMD_NFS | |
163 | /* | |
164 | * Board NAND Info. | |
165 | */ | |
166 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
167 | /* to access nand */ | |
168 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
169 | /* to access */ | |
170 | /* nand at CS0 */ | |
171 | ||
172 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ | |
173 | /* NAND devices */ | |
4ab779cb IY |
174 | #define CONFIG_JFFS2_NAND |
175 | /* nand device jffs2 lives on */ | |
176 | #define CONFIG_JFFS2_DEV "nand0" | |
177 | /* start of jffs2 partition */ | |
178 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
179 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ | |
180 | ||
181 | /* Environment information */ | |
8f1fae26 | 182 | #define CONFIG_BOOTDELAY 3 |
4ab779cb IY |
183 | |
184 | #define CONFIG_BOOTFILE "uImage" | |
185 | ||
f89a8b6a SB |
186 | #define xstr(s) str(s) |
187 | #define str(s) #s | |
188 | ||
189 | /* Setup MTD for NAND on the SOM */ | |
190 | #define MTDIDS_DEFAULT "nand0=omap2-nand.0" | |
191 | #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ | |
192 | "1m(u-boot),256k(env1)," \ | |
193 | "256k(env2),6m(kernel),6m(k_recovery)," \ | |
194 | "8m(fs_recovery),-(common_data)" | |
195 | ||
196 | #define CONFIG_HOSTNAME mcx | |
4ab779cb | 197 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
f89a8b6a SB |
198 | "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ |
199 | "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ | |
200 | "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ | |
201 | "addfb=setenv bootargs ${bootargs} vram=6M " \ | |
202 | "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ | |
203 | "addip_sta=setenv bootargs ${bootargs} " \ | |
204 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
205 | "${netmask}:${hostname}:eth0:off\0" \ | |
206 | "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ | |
207 | "addip=if test -n ${ipdyn};then run addip_dyn;" \ | |
208 | "else run addip_sta;fi\0" \ | |
209 | "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ | |
210 | "addtty=setenv bootargs ${bootargs} " \ | |
211 | "console=${consoledev},${baudrate}\0" \ | |
212 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
213 | "baudrate=115200\0" \ | |
214 | "consoledev=ttyO2\0" \ | |
215 | "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ | |
216 | "loadaddr=0x82000000\0" \ | |
217 | "load=tftp ${loadaddr} ${u-boot}\0" \ | |
218 | "load_k=tftp ${loadaddr} ${bootfile}\0" \ | |
219 | "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ | |
220 | "loadmlo=tftp ${loadaddr} ${mlo}\0" \ | |
221 | "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \ | |
222 | "mmcargs=root=/dev/mmcblk0p2 rw " \ | |
223 | "rootfstype=ext3 rootwait\0" \ | |
224 | "mmcboot=echo Booting from mmc ...; " \ | |
225 | "run mmcargs; " \ | |
226 | "run addip addtty addmtd addfb addeth addmisc;" \ | |
227 | "run loaduimage; " \ | |
228 | "bootm ${loadaddr}\0" \ | |
229 | "net_nfs=run load_k; " \ | |
230 | "run nfsargs; " \ | |
231 | "run addip addtty addmtd addfb addeth addmisc;" \ | |
232 | "bootm ${loadaddr}\0" \ | |
233 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
234 | "nfsroot=${serverip}:${rootpath}\0" \ | |
235 | "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \ | |
236 | "uboot_addr=0x80000\0" \ | |
237 | "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ | |
238 | "nand write ${loadaddr} ${uboot_addr} 80000\0" \ | |
239 | "updatemlo=nandecc hw;nand erase 0 20000;" \ | |
240 | "nand write ${loadaddr} 0 20000\0" \ | |
241 | "upd=if run load;then echo Updating u-boot;if run update;" \ | |
242 | "then echo U-Boot updated;" \ | |
243 | "else echo Error updating u-boot !;" \ | |
244 | "echo Board without bootloader !!;" \ | |
245 | "fi;" \ | |
246 | "else echo U-Boot not downloaded..exiting;fi\0" \ | |
247 | "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ | |
248 | "bootscript=echo Running bootscript from mmc ...; " \ | |
249 | "source ${loadaddr}\0" \ | |
250 | "nandargs=setenv bootargs ubi.mtd=7 " \ | |
251 | "root=ubi0:rootfs rootfstype=ubifs\0" \ | |
252 | "nandboot=echo Booting from nand ...; " \ | |
253 | "run nandargs; " \ | |
254 | "ubi part nand0,4;" \ | |
255 | "ubi readvol ${loadaddr} kernel;" \ | |
e47c9e86 | 256 | "run addtty addmtd addfb addeth addmisc;" \ |
f89a8b6a | 257 | "bootm ${loadaddr}\0" \ |
8f1fae26 SB |
258 | "preboot=ubi part nand0,7;" \ |
259 | "ubi readvol ${loadaddr} splash;" \ | |
260 | "bmp display ${loadaddr};" \ | |
261 | "gpio set 55\0" \ | |
e47c9e86 SB |
262 | "swupdate_args=setenv bootargs root=/dev/ram " \ |
263 | "quiet loglevel=1 " \ | |
264 | "consoleblank=0 ${swupdate_misc}\0" \ | |
f89a8b6a SB |
265 | "swupdate=echo Running Sw-Update...;" \ |
266 | "if printenv mtdparts;then echo Starting SwUpdate...; " \ | |
267 | "else mtdparts default;fi; " \ | |
268 | "ubi part nand0,5;" \ | |
269 | "ubi readvol 0x82000000 kernel_recovery;" \ | |
e47c9e86 SB |
270 | "ubi part nand0,6;" \ |
271 | "ubi readvol 0x84000000 fs_recovery;" \ | |
f89a8b6a SB |
272 | "run swupdate_args; " \ |
273 | "setenv bootargs ${bootargs} " \ | |
274 | "${mtdparts} " \ | |
275 | "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ | |
276 | "omapdss.def_disp=lcd;" \ | |
e47c9e86 | 277 | "bootm 0x82000000 0x84000000\0" |
4ab779cb IY |
278 | |
279 | #define CONFIG_BOOTCOMMAND \ | |
f89a8b6a | 280 | "run nandboot" |
4ab779cb IY |
281 | |
282 | #define CONFIG_AUTO_COMPLETE | |
48a4ee50 DZ |
283 | #define CONFIG_CMDLINE_EDITING |
284 | ||
4ab779cb IY |
285 | /* |
286 | * Miscellaneous configurable options | |
287 | */ | |
288 | #define V_PROMPT "mcx # " | |
289 | ||
290 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
291 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
4ab779cb | 292 | #define CONFIG_SYS_PROMPT V_PROMPT |
992a27d5 | 293 | #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ |
4ab779cb IY |
294 | /* Print Buffer Size */ |
295 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
296 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
297 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
298 | /* args */ | |
299 | /* Boot Argument Buffer Size */ | |
300 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
301 | /* memtest works on */ | |
302 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
303 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
304 | 0x01F00000) /* 31MB */ | |
305 | ||
306 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ | |
307 | /* address */ | |
8f1fae26 | 308 | #define CONFIG_PREBOOT |
4ab779cb IY |
309 | |
310 | /* | |
311 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
312 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
313 | * This rate is divided by a local divisor. | |
314 | */ | |
315 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 | |
316 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
317 | #define CONFIG_SYS_HZ 1000 | |
318 | ||
4ab779cb IY |
319 | /* |
320 | * Physical Memory Map | |
321 | */ | |
322 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
323 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
4ab779cb IY |
324 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
325 | ||
326 | /* | |
327 | * FLASH and environment organization | |
328 | */ | |
329 | ||
330 | /* **** PISMO SUPPORT *** */ | |
331 | ||
332 | /* Configure the PISMO */ | |
333 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
334 | ||
335 | #define CONFIG_NAND_OMAP_GPMC | |
336 | #define GPMC_NAND_ECC_LP_x16_LAYOUT | |
337 | #define CONFIG_ENV_IS_IN_NAND | |
f89a8b6a | 338 | #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ |
4ab779cb | 339 | |
f89a8b6a | 340 | /* Redundant Environment */ |
4ab779cb IY |
341 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
342 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
343 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
f89a8b6a SB |
344 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ |
345 | 2 * CONFIG_SYS_ENV_SECT_SIZE) | |
346 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
4ab779cb IY |
347 | |
348 | /* Flash banks JFFS2 should use */ | |
349 | #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ | |
350 | CONFIG_SYS_MAX_NAND_DEVICE) | |
351 | #define CONFIG_SYS_JFFS2_MEM_NAND | |
352 | /* use flash_info[2] */ | |
353 | #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS | |
354 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
355 | ||
356 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
357 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
358 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
359 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
360 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
361 | GENERATED_GBL_DATA_SIZE) | |
362 | ||
363 | /* Defines for SPL */ | |
364 | #define CONFIG_SPL | |
47f7bcae | 365 | #define CONFIG_SPL_FRAMEWORK |
d7cb93b2 | 366 | #define CONFIG_SPL_BOARD_INIT |
4ab779cb IY |
367 | #define CONFIG_SPL_NAND_SIMPLE |
368 | #define CONFIG_SPL_NAND_SOFTECC | |
369 | ||
370 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
371 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
372 | #define CONFIG_SPL_I2C_SUPPORT | |
373 | #define CONFIG_SPL_MMC_SUPPORT | |
374 | #define CONFIG_SPL_FAT_SUPPORT | |
375 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
376 | #define CONFIG_SPL_SERIAL_SUPPORT | |
377 | #define CONFIG_SPL_POWER_SUPPORT | |
378 | #define CONFIG_SPL_NAND_SUPPORT | |
6f2f01b9 SW |
379 | #define CONFIG_SPL_NAND_BASE |
380 | #define CONFIG_SPL_NAND_DRIVERS | |
381 | #define CONFIG_SPL_NAND_ECC | |
4ab779cb IY |
382 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" |
383 | ||
384 | #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ | |
e0820ccc | 385 | #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ |
4ab779cb IY |
386 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
387 | ||
388 | /* move malloc and bss high to prevent clashing with the main image */ | |
389 | #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 | |
390 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 | |
391 | #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ | |
392 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
393 | ||
394 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ | |
395 | #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 | |
396 | #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" | |
397 | ||
398 | /* NAND boot config */ | |
399 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
400 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
401 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
402 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
403 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
404 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
405 | #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ | |
406 | 48, 49, 50, 51, 52, 53, 54, 55,\ | |
407 | 56, 57, 58, 59, 60, 61, 62, 63} | |
408 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
409 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
410 | ||
4ab779cb IY |
411 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
412 | ||
413 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
414 | ||
415 | /* | |
416 | * ethernet support | |
417 | * | |
418 | */ | |
419 | #if defined(CONFIG_CMD_NET) | |
420 | #define CONFIG_DRIVER_TI_EMAC | |
421 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII | |
422 | #define CONFIG_MII | |
423 | #define CONFIG_BOOTP_DEFAULT | |
424 | #define CONFIG_BOOTP_DNS | |
425 | #define CONFIG_BOOTP_DNS2 | |
426 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
427 | #define CONFIG_NET_RETRY_COUNT 10 | |
428 | #endif | |
429 | ||
8f1fae26 SB |
430 | #define CONFIG_VIDEO |
431 | #define CONFIG_CFB_CONSOLE | |
432 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
433 | #define CONFIG_SPLASH_SCREEN | |
434 | #define CONFIG_VIDEO_BMP_RLE8 | |
435 | #define CONFIG_CMD_BMP | |
436 | #define CONFIG_VIDEO_OMAP3 | |
437 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
438 | ||
4ab779cb | 439 | #endif /* __CONFIG_H */ |