[people/ms/u-boot.git] / include / configs / mcx.h

/*
 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
 *
 * Based on omap3_evm_config.h
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP3_MCX		/* working with mcx */
#define CONFIG_OMAP_GPIO

#define CONFIG_MACH_TYPE	MACH_TYPE_MCX

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/*
 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
 * and older u-boot.bin with the new U-Boot SPL.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
/*
 * DDR related
 */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* EHCI */
#define CONFIG_OMAP3_GPIO_2
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define	CONFIG_USB_HOST_ETHER
#define	CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830

/* commands to include */
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS

#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/* RTC */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR		0x68

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

/* Environment information */

#define CONFIG_BOOTFILE		"uImage"

/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
				"1m(u-boot),256k(env1),"		\
				"256k(env2),6m(kernel),6m(k_recovery),"	\
				"8m(fs_recovery),-(common_data)"

#define CONFIG_HOSTNAME mcx
#define CONFIG_EXTRA_ENV_SETTINGS \
	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
	"addfb=setenv bootargs ${bootargs} vram=6M "			\
		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
		"${netmask}:${hostname}:eth0:off\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"addtty=setenv bootargs ${bootargs} "				\
		"console=${consoledev},${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"baudrate=115200\0"						\
	"consoledev=ttyO2\0"						\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"loadaddr=0x82000000\0"						\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
	"mmcargs=root=/dev/mmcblk0p2 rw "				\
		"rootfstype=ext3 rootwait\0"				\
	"mmcboot=echo Booting from mmc ...; "				\
		"run mmcargs; "						\
		"run addip addtty addmtd addfb addeth addmisc;"		\
		"run loaduimage; "					\
		"bootm ${loadaddr}\0"					\
	"net_nfs=run load_k; "						\
		"run nfsargs; "						\
		"run addip addtty addmtd addfb addeth addmisc;"		\
		"bootm ${loadaddr}\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
	"uboot_addr=0x80000\0"						\
	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
	"updatemlo=nandecc hw;nand erase 0 20000;"			\
		"nand write ${loadaddr} 0 20000\0"			\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
	"bootscript=echo Running bootscript from mmc ...; "		\
		"source ${loadaddr}\0"					\
	"nandargs=setenv bootargs ubi.mtd=7 "				\
		"root=ubi0:rootfs rootfstype=ubifs\0"			\
	"nandboot=echo Booting from nand ...; "				\
		"run nandargs; "					\
		"ubi part nand0,4;"					\
		"ubi readvol ${loadaddr} kernel;"			\
		"run addtty addmtd addfb addeth addmisc;"		\
		"bootm ${loadaddr}\0"					\
	"preboot=ubi part nand0,7;"					\
		"ubi readvol ${loadaddr} splash;"			\
		"bmp display ${loadaddr};"				\
		"gpio set 55\0"						\
	"swupdate_args=setenv bootargs root=/dev/ram "			\
		"quiet loglevel=1 "					\
		"consoleblank=0 ${swupdate_misc}\0"			\
	"swupdate=echo Running Sw-Update...;"				\
		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
		"else mtdparts default;fi; "				\
		"ubi part nand0,5;"					\
		"ubi readvol 0x82000000 kernel_recovery;"		\
		"ubi part nand0,6;"					\
		"ubi readvol 0x84000000 fs_recovery;"			\
		"run swupdate_args; "					\
		"setenv bootargs ${bootargs} "				\
			"${mtdparts} "					\
			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
			"omapdss.def_disp=lcd;"				\
		"bootm 0x82000000 0x84000000\0"				\
	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
		"then source 82000000;else run nandboot;fi\0"

#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */
#define CONFIG_PREBOOT

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#define CONFIG_NAND
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */

/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE

#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

/* move malloc and bss high to prevent clashing with the main image */
#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
					 48, 49, 50, 51, 52, 53, 54, 55,\
					 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SPL_NAND_SOFTECC

#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * ethernet support
 *
 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif

#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_OMAP3

#endif /* __CONFIG_H */
Commit	Line	Data
4ab779cb IY	1	/*
	2	* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
	3	*
	4	* Based on omap3_evm_config.h
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
4ab779cb IY	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Configuration Options
	14	*/
4ab779cb	15	#define CONFIG_OMAP3_MCX /* working with mcx */
308252ad	16	#define CONFIG_OMAP_GPIO
4ab779cb	17
4ab779cb IY	18	#define CONFIG_MACH_TYPE MACH_TYPE_MCX
4ab779cb IY	19
4ab779cb IY	20	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	21
	22	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	23	#include <asm/arch/omap.h>
4ab779cb	24
4ab779cb IY	25	/*
	26	* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
	27	* and older u-boot.bin with the new U-Boot SPL.
	28	*/
	29	#define CONFIG_SYS_TEXT_BASE 0x80008000
	30
4ab779cb IY	31	/* Clock Defines */
	32	#define V_OSCK 26000000 /* Clock output from T2 */
	33	#define V_SCLK (V_OSCK >> 1)
	34
	35	#define CONFIG_MISC_INIT_R
	36
	37	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	38	#define CONFIG_SETUP_MEMORY_TAGS
	39	#define CONFIG_INITRD_TAG
	40	#define CONFIG_REVISION_TAG
	41
	42	/*
	43	* Size of malloc() pool
	44	*/
	45	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	46	#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
	47	/*
	48	* DDR related
	49	*/
	50	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	51
	52	/*
	53	* Hardware drivers
	54	*/
	55
	56	/*
	57	* NS16550 Configuration
	58	*/
	59	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	60
4ab779cb IY	61	#define CONFIG_SYS_NS16550_SERIAL
	62	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	63	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	64
	65	/*
	66	* select serial console configuration
	67	*/
	68	#define CONFIG_CONS_INDEX 3
	69	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	70	#define CONFIG_SERIAL3 3 /* UART3 */
	71
	72	/* allow to overwrite serial and ethaddr */
	73	#define CONFIG_ENV_OVERWRITE
4ab779cb IY	74	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
4ab779cb IY	75	115200}
4ab779cb IY	76
4ab779cb IY	77	/* EHCI */
92671102	78	#define CONFIG_OMAP3_GPIO_2
4ab779cb IY	79	#define CONFIG_OMAP3_GPIO_5
	80	#define CONFIG_USB_EHCI
	81	#define CONFIG_USB_EHCI_OMAP
8c735b99	82	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
4ab779cb	83	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
01d10aa1 SB	84	#define CONFIG_USB_HOST_ETHER
	85	#define CONFIG_USB_ETHER_ASIX
	86	#define CONFIG_USB_ETHER_MCS7830
4ab779cb IY	87
4ab779cb IY	88	/* commands to include */
4ab779cb IY	89	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
4ab779cb IY	90
4ab779cb	91	#define CONFIG_CMD_NAND /* NAND support */
4ab779cb IY	92	#define CONFIG_CMD_UBIFS
	93	#define CONFIG_RBTREE
	94	#define CONFIG_LZO
	95	#define CONFIG_MTD_PARTITIONS
	96	#define CONFIG_MTD_DEVICE
	97	#define CONFIG_CMD_MTDPARTS
	98
6789e84e HS	99	#define CONFIG_SYS_I2C
	100	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	101	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	102	#define CONFIG_SYS_I2C_OMAP34XX
4ab779cb IY	103
	104	/* RTC */
	105	#define CONFIG_RTC_DS1337
	106	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	107
4ab779cb IY	108	/*
	109	* Board NAND Info.
	110	*/
	111	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	112	/* to access nand */
	113	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	114	/* to access */
	115	/* nand at CS0 */
	116
	117	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	118	/* NAND devices */
4ab779cb IY	119	#define CONFIG_JFFS2_NAND
	120	/* nand device jffs2 lives on */
	121	#define CONFIG_JFFS2_DEV "nand0"
	122	/* start of jffs2 partition */
	123	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	124	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	125
	126	/* Environment information */
4ab779cb IY	127
	128	#define CONFIG_BOOTFILE "uImage"
	129
f89a8b6a SB	130	/* Setup MTD for NAND on the SOM */
	131	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	132	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
	133	"1m(u-boot),256k(env1)," \
	134	"256k(env2),6m(kernel),6m(k_recovery)," \
	135	"8m(fs_recovery),-(common_data)"
	136
	137	#define CONFIG_HOSTNAME mcx
4ab779cb	138	#define CONFIG_EXTRA_ENV_SETTINGS \
f89a8b6a SB	139	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
	140	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
	141	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
	142	"addfb=setenv bootargs ${bootargs} vram=6M " \
	143	"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
	144	"addip_sta=setenv bootargs ${bootargs} " \
	145	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	146	"${netmask}:${hostname}:eth0:off\0" \
	147	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	148	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	149	"else run addip_sta;fi\0" \
	150	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	151	"addtty=setenv bootargs ${bootargs} " \
	152	"console=${consoledev},${baudrate}\0" \
	153	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	154	"baudrate=115200\0" \
	155	"consoledev=ttyO2\0" \
4a8c3f69	156	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
f89a8b6a SB	157	"loadaddr=0x82000000\0" \
	158	"load=tftp ${loadaddr} ${u-boot}\0" \
	159	"load_k=tftp ${loadaddr} ${bootfile}\0" \
	160	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	161	"loadmlo=tftp ${loadaddr} ${mlo}\0" \
4a8c3f69	162	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
f89a8b6a SB	163	"mmcargs=root=/dev/mmcblk0p2 rw " \
	164	"rootfstype=ext3 rootwait\0" \
	165	"mmcboot=echo Booting from mmc ...; " \
	166	"run mmcargs; " \
	167	"run addip addtty addmtd addfb addeth addmisc;" \
	168	"run loaduimage; " \
	169	"bootm ${loadaddr}\0" \
	170	"net_nfs=run load_k; " \
	171	"run nfsargs; " \
	172	"run addip addtty addmtd addfb addeth addmisc;" \
	173	"bootm ${loadaddr}\0" \
	174	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	175	"nfsroot=${serverip}:${rootpath}\0" \
4a8c3f69	176	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
f89a8b6a SB	177	"uboot_addr=0x80000\0" \
	178	"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
	179	"nand write ${loadaddr} ${uboot_addr} 80000\0" \
	180	"updatemlo=nandecc hw;nand erase 0 20000;" \
	181	"nand write ${loadaddr} 0 20000\0" \
	182	"upd=if run load;then echo Updating u-boot;if run update;" \
	183	"then echo U-Boot updated;" \
	184	"else echo Error updating u-boot !;" \
	185	"echo Board without bootloader !!;" \
	186	"fi;" \
	187	"else echo U-Boot not downloaded..exiting;fi\0" \
	188	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	189	"bootscript=echo Running bootscript from mmc ...; " \
	190	"source ${loadaddr}\0" \
	191	"nandargs=setenv bootargs ubi.mtd=7 " \
	192	"root=ubi0:rootfs rootfstype=ubifs\0" \
	193	"nandboot=echo Booting from nand ...; " \
	194	"run nandargs; " \
	195	"ubi part nand0,4;" \
	196	"ubi readvol ${loadaddr} kernel;" \
e47c9e86	197	"run addtty addmtd addfb addeth addmisc;" \
f89a8b6a	198	"bootm ${loadaddr}\0" \
8f1fae26 SB	199	"preboot=ubi part nand0,7;" \
	200	"ubi readvol ${loadaddr} splash;" \
	201	"bmp display ${loadaddr};" \
	202	"gpio set 55\0" \
e47c9e86 SB	203	"swupdate_args=setenv bootargs root=/dev/ram " \
	204	"quiet loglevel=1 " \
	205	"consoleblank=0 ${swupdate_misc}\0" \
f89a8b6a SB	206	"swupdate=echo Running Sw-Update...;" \
	207	"if printenv mtdparts;then echo Starting SwUpdate...; " \
	208	"else mtdparts default;fi; " \
	209	"ubi part nand0,5;" \
	210	"ubi readvol 0x82000000 kernel_recovery;" \
e47c9e86 SB	211	"ubi part nand0,6;" \
e47c9e86 SB	212	"ubi readvol 0x84000000 fs_recovery;" \
f89a8b6a SB	213	"run swupdate_args; " \
	214	"setenv bootargs ${bootargs} " \
	215	"${mtdparts} " \
	216	"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
	217	"omapdss.def_disp=lcd;" \
a5d64dbf SB	218	"bootm 0x82000000 0x84000000\0" \
	219	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
	220	"then source 82000000;else run nandboot;fi\0"
4ab779cb IY	221
4ab779cb IY	222	#define CONFIG_AUTO_COMPLETE
48a4ee50 DZ	223	#define CONFIG_CMDLINE_EDITING
48a4ee50 DZ	224
4ab779cb IY	225	/*
	226	* Miscellaneous configurable options
	227	*/
4ab779cb	228	#define CONFIG_SYS_LONGHELP /* undef to save memory */
992a27d5	229	#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
4ab779cb IY	230	/* Print Buffer Size */
	231	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	232	sizeof(CONFIG_SYS_PROMPT) + 16)
	233	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	234	/* args */
	235	/* Boot Argument Buffer Size */
	236	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	237	/* memtest works on */
	238	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	239	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	240	0x01F00000) /* 31MB */
	241
	242	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	243	/* address */
8f1fae26	244	#define CONFIG_PREBOOT
4ab779cb IY	245
	246	/*
	247	* AM3517 has 12 GP timers, they can be driven by the system clock
	248	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	249	* This rate is divided by a local divisor.
	250	*/
	251	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	252	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
4ab779cb	253
4ab779cb IY	254	/*
	255	* Physical Memory Map
	256	*/
	257	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	258	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
4ab779cb IY	259	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	260
	261	/*
	262	* FLASH and environment organization
	263	*/
	264
	265	/* ** PISMO SUPPORT * */
62321e2f SB	266	#define CONFIG_NAND
62321e2f SB	267	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
4ab779cb	268	#define CONFIG_NAND_OMAP_GPMC
62321e2f	269	#define CONFIG_NAND_OMAP_GPMC_PREFETCH
4ab779cb	270	#define CONFIG_ENV_IS_IN_NAND
f89a8b6a	271	#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
4ab779cb	272
f89a8b6a	273	/* Redundant Environment */
4ab779cb IY	274	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	275	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	276	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
f89a8b6a SB	277	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	278	2 * CONFIG_SYS_ENV_SECT_SIZE)
	279	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
4ab779cb IY	280
	281	/* Flash banks JFFS2 should use */
	282	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	283	CONFIG_SYS_MAX_NAND_DEVICE)
	284	#define CONFIG_SYS_JFFS2_MEM_NAND
	285	/* use flash_info[2] */
	286	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	287	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	288
	289	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	290	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	291	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	292	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	293	CONFIG_SYS_INIT_RAM_SIZE - \
	294	GENERATED_GBL_DATA_SIZE)
	295
	296	/* Defines for SPL */
47f7bcae	297	#define CONFIG_SPL_FRAMEWORK
d7cb93b2	298	#define CONFIG_SPL_BOARD_INIT
4ab779cb	299	#define CONFIG_SPL_NAND_SIMPLE
4ab779cb	300
6f2f01b9 SW	301	#define CONFIG_SPL_NAND_BASE
	302	#define CONFIG_SPL_NAND_DRIVERS
	303	#define CONFIG_SPL_NAND_ECC
983e3700	304	#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
4ab779cb IY	305
4ab779cb IY	306	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
e0820ccc	307	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
4ab779cb IY	308	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	309
	310	/* move malloc and bss high to prevent clashing with the main image */
	311	#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	312	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	313	#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	314	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	315
e2ccdf89	316	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	317	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
4ab779cb IY	318
	319	/* NAND boot config */
	320	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	321	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	322	#define CONFIG_SYS_NAND_OOBSIZE 64
	323	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	324	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	325	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	326	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	327	48, 49, 50, 51, 52, 53, 54, 55,\
	328	56, 57, 58, 59, 60, 61, 62, 63}
	329	#define CONFIG_SYS_NAND_ECCSIZE 256
	330	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	331	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
92671102	332	#define CONFIG_SPL_NAND_SOFTECC
4ab779cb	333
4ab779cb IY	334	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	335
	336	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	337
	338	/*
	339	* ethernet support
	340	*
	341	*/
	342	#if defined(CONFIG_CMD_NET)
	343	#define CONFIG_DRIVER_TI_EMAC
	344	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	345	#define CONFIG_MII
4ab779cb IY	346	#define CONFIG_BOOTP_DNS
	347	#define CONFIG_BOOTP_DNS2
	348	#define CONFIG_BOOTP_SEND_HOSTNAME
	349	#define CONFIG_NET_RETRY_COUNT 10
	350	#endif
	351
8f1fae26 SB	352	#define CONFIG_SPLASH_SCREEN
8f1fae26 SB	353	#define CONFIG_VIDEO_BMP_RLE8
8f1fae26	354	#define CONFIG_VIDEO_OMAP3
8f1fae26	355
4ab779cb	356	#endif /* __CONFIG_H */