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8b7d1f0a SR |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | /************************************************************************* | |
26 | * (c) 2005 esd gmbh Hannover | |
27 | * | |
28 | * | |
29 | * from IceCube.h file | |
30 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
31 | * | |
32 | *************************************************************************/ | |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* | |
38 | * High Level Configuration Options | |
39 | * (easy to change) | |
40 | */ | |
41 | ||
42 | #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ | |
43 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
44 | #define CONFIG_ICECUBE 1 /* ... on IceCube board */ | |
45 | #define CONFIG_MECP5200 1 /* ... on MECP5200 board */ | |
46 | #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ | |
47 | ||
6d0f6bcf | 48 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
8b7d1f0a SR |
49 | |
50 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
51 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
52 | ||
31d82672 BB |
53 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
54 | ||
8b7d1f0a SR |
55 | /* |
56 | * Serial console configuration | |
57 | */ | |
58 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
59 | #if 0 /* test-only */ | |
60 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
61 | #else | |
62 | #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ | |
63 | #endif | |
6d0f6bcf | 64 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
8b7d1f0a | 65 | |
8b7d1f0a SR |
66 | #define CONFIG_MII |
67 | #if 0 /* test-only !!! */ | |
68 | #define CONFIG_NET_MULTI 1 | |
69 | #define CONFIG_EEPRO100 1 | |
6d0f6bcf | 70 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
8b7d1f0a SR |
71 | #define CONFIG_NS8382X 1 |
72 | #endif | |
73 | ||
8b7d1f0a SR |
74 | /* Partitions */ |
75 | #define CONFIG_MAC_PARTITION | |
76 | #define CONFIG_DOS_PARTITION | |
77 | ||
78 | /* USB */ | |
79 | #if 0 | |
80 | #define CONFIG_USB_OHCI | |
8b7d1f0a | 81 | #define CONFIG_USB_STORAGE |
8b7d1f0a SR |
82 | #endif |
83 | ||
d794cfef | 84 | |
7f5c0157 JL |
85 | /* |
86 | * BOOTP options | |
87 | */ | |
88 | #define CONFIG_BOOTP_BOOTFILESIZE | |
89 | #define CONFIG_BOOTP_BOOTPATH | |
90 | #define CONFIG_BOOTP_GATEWAY | |
91 | #define CONFIG_BOOTP_HOSTNAME | |
92 | ||
93 | ||
8b7d1f0a | 94 | /* |
d794cfef | 95 | * Command line configuration. |
8b7d1f0a | 96 | */ |
d794cfef JL |
97 | #include <config_cmd_default.h> |
98 | ||
99 | #define CONFIG_CMD_EEPROM | |
100 | #define CONFIG_CMD_FAT | |
101 | #define CONFIG_CMD_EXT2 | |
102 | #define CONFIG_CMD_I2C | |
103 | #define CONFIG_CMD_IDE | |
104 | #define CONFIG_CMD_BSP | |
105 | #define CONFIG_CMD_ELF | |
106 | ||
8b7d1f0a SR |
107 | |
108 | #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ | |
6d0f6bcf JCPV |
109 | # define CONFIG_SYS_LOWBOOT 1 |
110 | # define CONFIG_SYS_LOWBOOT16 1 | |
8b7d1f0a SR |
111 | #endif |
112 | #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ | |
6d0f6bcf JCPV |
113 | # define CONFIG_SYS_LOWBOOT 1 |
114 | # define CONFIG_SYS_LOWBOOT08 1 | |
8b7d1f0a SR |
115 | #endif |
116 | ||
117 | /* | |
118 | * Autobooting | |
119 | */ | |
120 | #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ | |
121 | ||
122 | #define CONFIG_PREBOOT "echo;" \ | |
123 | "echo Welcome to CBX-CPU5200 (mecp5200);" \ | |
124 | "echo" | |
125 | ||
126 | #undef CONFIG_BOOTARGS | |
127 | ||
128 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
129 | "netdev=eth0\0" \ | |
74357114 WD |
130 | "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ |
131 | "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ | |
132 | "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \ | |
133 | "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \ | |
134 | "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \ | |
135 | "loadaddr=01000000\0" \ | |
136 | "serverip=192.168.2.99\0" \ | |
137 | "gatewayip=10.0.0.79\0" \ | |
138 | "user=mu\0" \ | |
139 | "target=mecp5200.esd\0" \ | |
140 | "script=mecp5200.bat\0" \ | |
141 | "image=/tftpboot/vxWorks_mecp5200\0" \ | |
142 | "ipaddr=10.0.13.196\0" \ | |
143 | "netmask=255.255.0.0\0" \ | |
8b7d1f0a SR |
144 | "" |
145 | ||
146 | #define CONFIG_BOOTCOMMAND "run flash_vxworks0" | |
147 | ||
8b7d1f0a SR |
148 | /* |
149 | * IPB Bus clocking configuration. | |
150 | */ | |
6d0f6bcf | 151 | #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ |
8b7d1f0a SR |
152 | /* |
153 | * I2C configuration | |
154 | */ | |
155 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 156 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
8b7d1f0a | 157 | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ |
159 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
8b7d1f0a SR |
160 | |
161 | /* | |
162 | * EEPROM configuration | |
163 | */ | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
165 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
166 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
167 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
168 | #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 | |
8b7d1f0a SR |
169 | /* |
170 | * Flash configuration | |
171 | */ | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 |
173 | #define CONFIG_SYS_FLASH_SIZE 0x00400000 | |
174 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000) | |
175 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
176 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
8b7d1f0a | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
179 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
8b7d1f0a SR |
180 | |
181 | /* | |
182 | * Environment settings | |
183 | */ | |
184 | #if 1 /* test-only */ | |
5a1aceb0 | 185 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
186 | #define CONFIG_ENV_SIZE 0x10000 |
187 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
8b7d1f0a SR |
188 | #define CONFIG_ENV_OVERWRITE 1 |
189 | #else | |
bb1f8b4f | 190 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
191 | #define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ |
192 | #define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/ | |
8b7d1f0a SR |
193 | /* total size of a CAT24WC32 is 8192 bytes */ |
194 | #define CONFIG_ENV_OVERWRITE 1 | |
195 | #endif | |
196 | ||
00b1883a | 197 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
199 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
8b7d1f0a | 200 | #if 0 |
6d0f6bcf | 201 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
8b7d1f0a | 202 | #endif |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */ |
204 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
205 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ | |
8b7d1f0a SR |
206 | |
207 | ||
208 | /* | |
209 | * Memory map | |
210 | */ | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_MBAR 0xF0000000 |
212 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
213 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
8b7d1f0a SR |
214 | |
215 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
217 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
8b7d1f0a SR |
218 | |
219 | ||
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
221 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
222 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
8b7d1f0a | 223 | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
225 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
226 | # define CONFIG_SYS_RAMBOOT 1 | |
8b7d1f0a SR |
227 | #endif |
228 | ||
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
230 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
231 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
8b7d1f0a SR |
232 | |
233 | /* | |
234 | * Ethernet configuration | |
235 | */ | |
236 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 237 | #define CONFIG_MPC5xxx_FEC_MII100 |
8b7d1f0a | 238 | /* |
86321fc1 | 239 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
8b7d1f0a | 240 | */ |
86321fc1 | 241 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
8b7d1f0a SR |
242 | #define CONFIG_PHY_ADDR 0x00 |
243 | #define CONFIG_UDP_CHECKSUM 1 | |
244 | ||
245 | ||
246 | /* | |
247 | * GPIO configuration | |
248 | */ | |
6d0f6bcf | 249 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 |
8b7d1f0a SR |
250 | |
251 | /* | |
252 | * Miscellaneous configurable options | |
253 | */ | |
6d0f6bcf JCPV |
254 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
255 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
d794cfef | 256 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 257 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8b7d1f0a | 258 | #else |
6d0f6bcf | 259 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8b7d1f0a | 260 | #endif |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
262 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
263 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8b7d1f0a | 264 | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
266 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
8b7d1f0a | 267 | |
6d0f6bcf | 268 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
8b7d1f0a | 269 | |
6d0f6bcf | 270 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
8b7d1f0a | 271 | |
6d0f6bcf | 272 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
8b7d1f0a | 273 | |
6d0f6bcf | 274 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
d794cfef | 275 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 276 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
d794cfef JL |
277 | #endif |
278 | ||
8b7d1f0a SR |
279 | /* |
280 | * Various low-level settings | |
281 | */ | |
6d0f6bcf JCPV |
282 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
283 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
8b7d1f0a | 284 | |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
286 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
287 | #define CONFIG_SYS_BOOTCS_CFG 0x00085d00 | |
8b7d1f0a | 288 | |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
290 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
8b7d1f0a | 291 | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_CS1_START 0xfd000000 |
293 | #define CONFIG_SYS_CS1_SIZE 0x00010000 | |
294 | #define CONFIG_SYS_CS1_CFG 0x10101410 | |
8b7d1f0a | 295 | |
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_CS_BURST 0x00000000 |
297 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
8b7d1f0a | 298 | |
6d0f6bcf | 299 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
8b7d1f0a SR |
300 | |
301 | /*----------------------------------------------------------------------- | |
302 | * USB stuff | |
303 | *----------------------------------------------------------------------- | |
304 | */ | |
305 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
306 | #define CONFIG_USB_CONFIG 0x00001000 | |
307 | ||
308 | /*----------------------------------------------------------------------- | |
309 | * IDE/ATA stuff Supports IDE harddisk | |
310 | *----------------------------------------------------------------------- | |
311 | */ | |
312 | ||
313 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
314 | ||
315 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
316 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
317 | ||
318 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
319 | #define CONFIG_IDE_PREINIT | |
320 | ||
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
322 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
8b7d1f0a | 323 | |
6d0f6bcf | 324 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
8b7d1f0a | 325 | |
6d0f6bcf | 326 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
8b7d1f0a SR |
327 | |
328 | /* Offset for data I/O */ | |
6d0f6bcf | 329 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
8b7d1f0a SR |
330 | |
331 | /* Offset for normal register accesses */ | |
6d0f6bcf | 332 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
8b7d1f0a SR |
333 | |
334 | /* Offset for alternate registers */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
8b7d1f0a | 336 | |
74357114 | 337 | /* Interval between registers */ |
6d0f6bcf | 338 | #define CONFIG_SYS_ATA_STRIDE 4 |
8b7d1f0a SR |
339 | |
340 | #endif /* __CONFIG_H */ |