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8b7d1f0a SR |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
8b7d1f0a SR |
6 | */ |
7 | ||
8 | ||
9 | /************************************************************************* | |
10 | * (c) 2005 esd gmbh Hannover | |
11 | * | |
12 | * | |
13 | * from IceCube.h file | |
14 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
15 | * | |
16 | *************************************************************************/ | |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
21 | /* | |
22 | * High Level Configuration Options | |
23 | * (easy to change) | |
24 | */ | |
25 | ||
b2a6dfe4 | 26 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
8b7d1f0a SR |
27 | #define CONFIG_ICECUBE 1 /* ... on IceCube board */ |
28 | #define CONFIG_MECP5200 1 /* ... on MECP5200 board */ | |
29 | #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ | |
30 | ||
2ae18241 WD |
31 | #ifndef CONFIG_SYS_TEXT_BASE |
32 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
33 | #endif | |
34 | ||
6d0f6bcf | 35 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
8b7d1f0a | 36 | |
31d82672 BB |
37 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
38 | ||
8b7d1f0a SR |
39 | /* |
40 | * Serial console configuration | |
41 | */ | |
42 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
43 | #if 0 /* test-only */ | |
44 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
45 | #else | |
46 | #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ | |
47 | #endif | |
6d0f6bcf | 48 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
8b7d1f0a | 49 | |
8b7d1f0a SR |
50 | #define CONFIG_MII |
51 | #if 0 /* test-only !!! */ | |
8b7d1f0a | 52 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 53 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
8b7d1f0a SR |
54 | #define CONFIG_NS8382X 1 |
55 | #endif | |
56 | ||
8b7d1f0a SR |
57 | /* Partitions */ |
58 | #define CONFIG_MAC_PARTITION | |
59 | #define CONFIG_DOS_PARTITION | |
60 | ||
61 | /* USB */ | |
62 | #if 0 | |
63 | #define CONFIG_USB_OHCI | |
8b7d1f0a | 64 | #define CONFIG_USB_STORAGE |
8b7d1f0a SR |
65 | #endif |
66 | ||
d794cfef | 67 | |
7f5c0157 JL |
68 | /* |
69 | * BOOTP options | |
70 | */ | |
71 | #define CONFIG_BOOTP_BOOTFILESIZE | |
72 | #define CONFIG_BOOTP_BOOTPATH | |
73 | #define CONFIG_BOOTP_GATEWAY | |
74 | #define CONFIG_BOOTP_HOSTNAME | |
75 | ||
76 | ||
8b7d1f0a | 77 | /* |
d794cfef | 78 | * Command line configuration. |
8b7d1f0a | 79 | */ |
d794cfef JL |
80 | #include <config_cmd_default.h> |
81 | ||
82 | #define CONFIG_CMD_EEPROM | |
83 | #define CONFIG_CMD_FAT | |
84 | #define CONFIG_CMD_EXT2 | |
85 | #define CONFIG_CMD_I2C | |
86 | #define CONFIG_CMD_IDE | |
87 | #define CONFIG_CMD_BSP | |
88 | #define CONFIG_CMD_ELF | |
89 | ||
8b7d1f0a | 90 | |
14d0a02a | 91 | #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ |
6d0f6bcf JCPV |
92 | # define CONFIG_SYS_LOWBOOT 1 |
93 | # define CONFIG_SYS_LOWBOOT16 1 | |
8b7d1f0a | 94 | #endif |
14d0a02a | 95 | #if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ |
6d0f6bcf JCPV |
96 | # define CONFIG_SYS_LOWBOOT 1 |
97 | # define CONFIG_SYS_LOWBOOT08 1 | |
8b7d1f0a SR |
98 | #endif |
99 | ||
100 | /* | |
101 | * Autobooting | |
102 | */ | |
103 | #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ | |
104 | ||
105 | #define CONFIG_PREBOOT "echo;" \ | |
106 | "echo Welcome to CBX-CPU5200 (mecp5200);" \ | |
107 | "echo" | |
108 | ||
109 | #undef CONFIG_BOOTARGS | |
110 | ||
111 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
112 | "netdev=eth0\0" \ | |
74357114 WD |
113 | "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ |
114 | "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ | |
115 | "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \ | |
116 | "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \ | |
117 | "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \ | |
118 | "loadaddr=01000000\0" \ | |
119 | "serverip=192.168.2.99\0" \ | |
120 | "gatewayip=10.0.0.79\0" \ | |
121 | "user=mu\0" \ | |
122 | "target=mecp5200.esd\0" \ | |
123 | "script=mecp5200.bat\0" \ | |
124 | "image=/tftpboot/vxWorks_mecp5200\0" \ | |
125 | "ipaddr=10.0.13.196\0" \ | |
126 | "netmask=255.255.0.0\0" \ | |
8b7d1f0a SR |
127 | "" |
128 | ||
129 | #define CONFIG_BOOTCOMMAND "run flash_vxworks0" | |
130 | ||
8b7d1f0a SR |
131 | /* |
132 | * IPB Bus clocking configuration. | |
133 | */ | |
6d0f6bcf | 134 | #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ |
8b7d1f0a SR |
135 | /* |
136 | * I2C configuration | |
137 | */ | |
138 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 139 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
8b7d1f0a | 140 | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ |
142 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
8b7d1f0a SR |
143 | |
144 | /* | |
145 | * EEPROM configuration | |
146 | */ | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
148 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
149 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
150 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
151 | #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 | |
8b7d1f0a SR |
152 | /* |
153 | * Flash configuration | |
154 | */ | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 |
156 | #define CONFIG_SYS_FLASH_SIZE 0x00400000 | |
157 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000) | |
158 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
159 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
8b7d1f0a | 160 | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
162 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
8b7d1f0a SR |
163 | |
164 | /* | |
165 | * Environment settings | |
166 | */ | |
167 | #if 1 /* test-only */ | |
5a1aceb0 | 168 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
169 | #define CONFIG_ENV_SIZE 0x10000 |
170 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
8b7d1f0a SR |
171 | #define CONFIG_ENV_OVERWRITE 1 |
172 | #else | |
bb1f8b4f | 173 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
174 | #define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ |
175 | #define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/ | |
8b7d1f0a SR |
176 | /* total size of a CAT24WC32 is 8192 bytes */ |
177 | #define CONFIG_ENV_OVERWRITE 1 | |
178 | #endif | |
179 | ||
00b1883a | 180 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
182 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
8b7d1f0a | 183 | #if 0 |
6d0f6bcf | 184 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
8b7d1f0a | 185 | #endif |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */ |
187 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
188 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ | |
8b7d1f0a SR |
189 | |
190 | ||
191 | /* | |
192 | * Memory map | |
193 | */ | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_MBAR 0xF0000000 |
195 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
196 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
8b7d1f0a SR |
197 | |
198 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 199 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 200 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
8b7d1f0a SR |
201 | |
202 | ||
25ddd1fb | 203 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 204 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8b7d1f0a | 205 | |
14d0a02a | 206 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
207 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
208 | # define CONFIG_SYS_RAMBOOT 1 | |
8b7d1f0a SR |
209 | #endif |
210 | ||
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
212 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
213 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
8b7d1f0a SR |
214 | |
215 | /* | |
216 | * Ethernet configuration | |
217 | */ | |
218 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 219 | #define CONFIG_MPC5xxx_FEC_MII100 |
8b7d1f0a | 220 | /* |
86321fc1 | 221 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
8b7d1f0a | 222 | */ |
86321fc1 | 223 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
8b7d1f0a SR |
224 | #define CONFIG_PHY_ADDR 0x00 |
225 | #define CONFIG_UDP_CHECKSUM 1 | |
226 | ||
227 | ||
228 | /* | |
229 | * GPIO configuration | |
230 | */ | |
6d0f6bcf | 231 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 |
8b7d1f0a SR |
232 | |
233 | /* | |
234 | * Miscellaneous configurable options | |
235 | */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
d794cfef | 237 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 238 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8b7d1f0a | 239 | #else |
6d0f6bcf | 240 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8b7d1f0a | 241 | #endif |
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
243 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
244 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8b7d1f0a | 245 | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
247 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
8b7d1f0a | 248 | |
6d0f6bcf | 249 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
8b7d1f0a | 250 | |
6d0f6bcf | 251 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
8b7d1f0a | 252 | |
6d0f6bcf | 253 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
d794cfef | 254 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 255 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
d794cfef JL |
256 | #endif |
257 | ||
8b7d1f0a SR |
258 | /* |
259 | * Various low-level settings | |
260 | */ | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
262 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
8b7d1f0a | 263 | |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
265 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
266 | #define CONFIG_SYS_BOOTCS_CFG 0x00085d00 | |
8b7d1f0a | 267 | |
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
269 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
8b7d1f0a | 270 | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_CS1_START 0xfd000000 |
272 | #define CONFIG_SYS_CS1_SIZE 0x00010000 | |
273 | #define CONFIG_SYS_CS1_CFG 0x10101410 | |
8b7d1f0a | 274 | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_CS_BURST 0x00000000 |
276 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
8b7d1f0a | 277 | |
6d0f6bcf | 278 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
8b7d1f0a SR |
279 | |
280 | /*----------------------------------------------------------------------- | |
281 | * USB stuff | |
282 | *----------------------------------------------------------------------- | |
283 | */ | |
284 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
285 | #define CONFIG_USB_CONFIG 0x00001000 | |
286 | ||
287 | /*----------------------------------------------------------------------- | |
288 | * IDE/ATA stuff Supports IDE harddisk | |
289 | *----------------------------------------------------------------------- | |
290 | */ | |
291 | ||
292 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
293 | ||
294 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
295 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
296 | ||
297 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
298 | #define CONFIG_IDE_PREINIT | |
299 | ||
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
301 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
8b7d1f0a | 302 | |
6d0f6bcf | 303 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
8b7d1f0a | 304 | |
6d0f6bcf | 305 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
8b7d1f0a SR |
306 | |
307 | /* Offset for data I/O */ | |
6d0f6bcf | 308 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
8b7d1f0a SR |
309 | |
310 | /* Offset for normal register accesses */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
8b7d1f0a SR |
312 | |
313 | /* Offset for alternate registers */ | |
6d0f6bcf | 314 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
8b7d1f0a | 315 | |
74357114 | 316 | /* Interval between registers */ |
6d0f6bcf | 317 | #define CONFIG_SYS_ATA_STRIDE 4 |
8b7d1f0a SR |
318 | |
319 | #endif /* __CONFIG_H */ |