projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 33b1d3f4 DG |
2 | /* |
| 3 | * (C) Copyright 2007-2008 | |
| c9e798d3 | 4 | * Stelian Pop <stelian@popies.net> |
| 33b1d3f4 DG |
5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * | |
| 83bf0057 | 7 | * (C) Copyright 2009-2015 |
| 33b1d3f4 DG |
8 | * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> |
| 9 | * esd electronic system design gmbh <www.esd.eu> | |
| 10 | * | |
| 11 | * Configuation settings for the esd MEESC board. | |
| 33b1d3f4 DG |
12 | */ |
| 13 | ||
| 14 | #ifndef __CONFIG_H | |
| 15 | #define __CONFIG_H | |
| 16 | ||
| 0cb77bfa MF |
17 | /* |
| 18 | * SoC must be defined first, before hardware.h is included. | |
| 19 | * In this case SoC is defined in boards.cfg. | |
| 20 | */ | |
| 21 | #include <asm/hardware.h> | |
| 22 | ||
| 23 | /* | |
| 98463903 | 24 | * Warning: changing CONFIG_TEXT_BASE requires |
| 0cb77bfa MF |
25 | * adapting the initial boot program. |
| 26 | * Since the linker has to swallow that define, we must use a pure | |
| 27 | * hex number here! | |
| 28 | */ | |
| 0cb77bfa MF |
29 | |
| 30 | /* ARM asynchronous clock */ | |
| 31 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ | |
| 9f07dede | 32 | #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ |
| 33b1d3f4 | 33 | |
| 0cb77bfa | 34 | /* Misc CPU related */ |
| 33b1d3f4 | 35 | |
| 33b1d3f4 DG |
36 | /* |
| 37 | * Hardware drivers | |
| 38 | */ | |
| 39 | ||
| 0cb77bfa MF |
40 | /* |
| 41 | * SDRAM: 1 bank, min 32, max 128 MB | |
| 42 | * Initialized before u-boot gets started. | |
| 43 | */ | |
| 83bf0057 DG |
44 | #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ |
| 45 | #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ | |
| 46 | ||
| 83bf0057 DG |
47 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
| 48 | #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE | |
| 0cb77bfa | 49 | |
| eaf6ea6a TR |
50 | #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 |
| 51 | #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) | |
| 33b1d3f4 | 52 | |
| 33b1d3f4 DG |
53 | /* NAND flash */ |
| 54 | #ifdef CONFIG_CMD_NAND | |
| 0cb77bfa | 55 | # define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 83bf0057 | 56 | # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ |
| 0cb77bfa MF |
57 | # define CONFIG_SYS_NAND_DBW_8 |
| 58 | # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
| 59 | # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
| ac45bb16 AB |
60 | # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) |
| 61 | # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) | |
| 33b1d3f4 DG |
62 | #endif |
| 63 | ||
| a380279b | 64 | /* hw-controller addresses */ |
| 0cb77bfa MF |
65 | #define CONFIG_ET1100_BASE 0x70000000 |
| 66 | ||
| 33b1d3f4 | 67 | #endif |