[people/ms/u-boot.git] / include / configs / mgsuvd.h

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
#define CONFIG_MGSUVD		1	/* ...on a mgsuvd board	*/

/* Do boardspecific init */
#define CONFIG_BOARD_EARLY_INIT_R       1

#define CONFIG_8xx_GCLK_FREQ		66000000

#define CFG_SMC_UCODE_PATCH	1	/* Relocate SMC1 */
#define CFG_SMC_DPMEM_OFFSET	0x1fc0
#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_BOOTCOUNT_LIMIT

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS						\
	"netdev=eth0\0"								\
	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=${serverip}:${rootpath}\0"				\
	"ramargs=setenv bootargs root=/dev/ram rw\0"				\
	"addip=setenv bootargs ${bootargs} "					\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
		":${hostname}:${netdev}:off panic=1\0"				\
	"flash_nfs=run nfsargs addip;"						\
		"bootm ${kernel_addr}\0"					\
	"flash_self=run ramargs addip;"						\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"			\
	"net_nfs=tftp ${kernel_addr} ${bootfile}; "				\
		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;"	\
		"bootm ${kernel_addr} - ${fdt_addr}\0"				\
	"rootpath=/opt/eldk/ppc_8xx\0"						\
	"bootfile=/tftpboot/mgsuvd/uImage\0"					\
	"fdt_addr=400000\0"							\
	"kernel_addr=200000\0"							\
	"fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0"				\
	"load=tftp 200000 ${u-boot}\0"						\
	"update=protect off f0000000 +${filesize};"				\
		"erase f0000000 +${filesize};"					\
		"cp.b 200000 f0000000 ${filesize};"				\
		"protect on f0000000 +${filesize}\0"				\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/

#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xf0000000
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_FLASH_SIZE		32
#define CFG_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */


#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#define CFG_SYPCR	0xffffff89

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 */
#define CFG_SIUMCR	0x00610480

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	0x01800000
#define CFG_SCCR	0x01800000

#define CFG_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xf0000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing: Default value of OR0 after reset
 */
#define CFG_OR0_PRELIM	0xfe000954
#define CFG_BR0_PRELIM	0xf0000401

/*
 * BR1 and OR1 (SDRAM)
 *
 */
#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_MAX_SIZE		(64 << 20)	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00

#define CFG_OR1_PRELIM	0xfc000800
#define CFG_BR1_PRELIM	(0x000000C0 | 0x01)

#define CFG_MPTPR	0x0200
/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
   1 Write loop Cycle (not used), 1 Timer Loop Cycle */
#define CFG_MBMR	0x10964111
#define CFG_MAR		0x00000088

/*
 * 4096	Rows from SDRAM example configuration
 * 1000	factor s -> ms
 * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))

/* GPIO/PIGGY on CS3 initialization values
*/
#define CFG_PIGGY_BASE	(0x30000000)
#define CFG_OR3_PRELIM	(0xfe000d24)
#define CFG_BR3_PRELIM	(0x30000401)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CONFIG_SCC3_ENET
#define CONFIG_ETHPRIME		"SCC ETHERNET"
#define CONFIG_HAS_ETH0

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,866@0"
#define OF_SOC			"soc@fff00000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc/cpm/serial@a80"

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
#define CFG_I2C_SPEED		50000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#define I2C_SOFT_DECLARATIONS

/*
 * Software (bit-bang) I2C driver configuration
 */
#define I2C_BASE_DIR	(CFG_PIGGY_BASE + 0x04)
#define I2C_BASE_PORT	(CFG_PIGGY_BASE + 0x09)

#define SDA_BIT		0x40
#define SCL_BIT		0x80
#define SDA_CONF	0x1000
#define SCL_CONF	0x2000

#define I2C_ACTIVE	do {} while (0)
#define I2C_TRISTATE	do {} while (0)
#define I2C_READ	i2c_soft_read_pin ()
#define I2C_SDA(bit)	if(bit) { \
				*(unsigned short *)(I2C_BASE_DIR) &=  ~SDA_CONF; \
				} \
			else    { \
				*(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \
				*(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \
				}
#define I2C_SCL(bit)	if(bit) { \
				*(unsigned short *)(I2C_BASE_DIR) &=  ~SCL_CONF; \
				} \
			else    { \
				*(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \
				*(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \
				}
#define I2C_DELAY	udelay(50)	/* 1/4 I2C clock duration */

#define CONFIG_I2C_MULTI_BUS	1
#define CONFIG_I2C_CMD_TREE	1
#define CFG_MAX_I2C_BUS		2

/* EEprom support */
#define CFG_I2C_EEPROM_ADDR_LEN	1
#define CFG_I2C_MULTI_EEPROMS	1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
#define CONFIG_DTT_SENSORS	{0, 2, 4, 6}	/* Sensor addresses		*/
#define CFG_DTT_MAX_TEMP	70
#define CFG_DTT_LOW_TEMP	-30
#define CFG_DTT_HYSTERESIS	3
#define CFG_DTT_BUS_NUM		(CFG_MAX_I2C_BUS)

#endif	/* __CONFIG_H */
Commit	Line	Data
381e4e63 HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
	37	#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
	38
82afabfe HS	39	/* Do boardspecific init */
	40	#define CONFIG_BOARD_EARLY_INIT_R 1
	41
381e4e63 HS	42	#define CONFIG_8xx_GCLK_FREQ 66000000
	43
	44	#define CFG_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
	45	#define CFG_SMC_DPMEM_OFFSET 0x1fc0
	46	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	47
	48	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	49
	50	#define CONFIG_BOOTCOUNT_LIMIT
	51
	52	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	53
	54	#define CONFIG_BOARD_TYPES 1 /* support board types */
	55
	56	#define CONFIG_PREBOOT "echo;" \
32bf3d14	57	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
381e4e63 HS	58	"echo"
	59
	60	#undef CONFIG_BOOTARGS
	61
c61e033d DZ	62	#define CONFIG_EXTRA_ENV_SETTINGS \
c61e033d DZ	63	"netdev=eth0\0" \
f308572e	64	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
c61e033d DZ	65	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	66	"nfsroot=${serverip}:${rootpath}\0" \
	67	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	68	"addip=setenv bootargs ${bootargs} " \
	69	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	70	":${hostname}:${netdev}:off panic=1\0" \
	71	"flash_nfs=run nfsargs addip;" \
	72	"bootm ${kernel_addr}\0" \
	73	"flash_self=run ramargs addip;" \
	74	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	75	"net_nfs=tftp ${kernel_addr} ${bootfile}; " \
	76	"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
	77	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	78	"rootpath=/opt/eldk/ppc_8xx\0" \
	79	"bootfile=/tftpboot/mgsuvd/uImage\0" \
	80	"fdt_addr=400000\0" \
	81	"kernel_addr=200000\0" \
	82	"fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0" \
	83	"load=tftp 200000 ${u-boot}\0" \
	84	"update=protect off f0000000 +${filesize};" \
	85	"erase f0000000 +${filesize};" \
	86	"cp.b 200000 f0000000 ${filesize};" \
	87	"protect on f0000000 +${filesize}\0" \
381e4e63 HS	88	""
	89	#define CONFIG_BOOTCOMMAND "run flash_self"
	90
	91	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	92	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	93
	94	#undef CONFIG_WATCHDOG /* watchdog disabled */
	95
	96	/*
	97	* BOOTP options
	98	*/
	99	#define CONFIG_BOOTP_SUBNETMASK
	100	#define CONFIG_BOOTP_GATEWAY
	101	#define CONFIG_BOOTP_HOSTNAME
	102	#define CONFIG_BOOTP_BOOTPATH
	103	#define CONFIG_BOOTP_BOOTFILESIZE
	104
	105	#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
	106
	107	#define CONFIG_TIMESTAMP /* but print image timestmps */
	108
	109	/*
	110	* Command line configuration.
	111	*/
	112	#include <config_cmd_default.h>
	113
	114	#define CONFIG_CMD_ASKENV
	115	#define CONFIG_CMD_DHCP
e5e4edd9	116	#define CONFIG_CMD_DTT
f2202450	117	#define CONFIG_CMD_EEPROM
9661bf9d	118	#define CONFIG_CMD_I2C
381e4e63 HS	119	#define CONFIG_CMD_NFS
	120	#define CONFIG_CMD_PING
	121
	122	/*
	123	* Miscellaneous configurable options
	124	*/
	125	#define CFG_LONGHELP /* undef to save memory */
	126	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	127
	128	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	129	#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
	130	#ifdef CFG_HUSH_PARSER
	131	#define CFG_PROMPT_HUSH_PS2 "> "
	132	#endif
	133
	134	#if defined(CONFIG_CMD_KGDB)
	135	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	136	#else
	137	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	138	#endif
	139	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	140	#define CFG_MAXARGS 16 /* max number of command args */
	141	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	142
	143	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	144	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	145
	146	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	147
	148	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	149
	150	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	151
	152	/*
	153	* Low Level Configuration Settings
	154	* (address mappings, register initial values, etc.)
	155	* You should know what you are doing if you make changes here.
	156	*/
	157	/*-----------------------------------------------------------------------
	158	* Internal Memory Mapped Register
	159	*/
	160	#define CFG_IMMR 0xFFF00000
	161
	162	/*-----------------------------------------------------------------------
	163	* Definitions for initial stack pointer and data area (in DPRAM)
	164	*/
	165	#define CFG_INIT_RAM_ADDR CFG_IMMR
	166	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	167	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	168	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	169	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	170
	171	/*-----------------------------------------------------------------------
	172	* Start addresses for the final memory configuration
	173	* (Set up by the startup code)
	174	* Please note that CFG_SDRAM_BASE _must_ start at 0
	175	*/
	176	#define CFG_SDRAM_BASE 0x00000000
	177	#define CFG_FLASH_BASE 0xf0000000
	178	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	179	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	180	#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
	181
	182	/*
183	* For booting Linux, the board info and command line data
184	* have to be in the first 8 MB of memory, since this is
185	* the maximum mapped by the Linux kernel during initialization.
186	*/
187	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188
189	/*-----------------------------------------------------------------------
190	* FLASH organization
191	*/
192	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
193	#define CFG_FLASH_SIZE 32
194	#define CFG_FLASH_CFI
00b1883a	195	#define CONFIG_FLASH_CFI_DRIVER
381e4e63 HS	196	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	197
	198
	199	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	200	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	201
5a1aceb0	202	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	203	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	204	#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
	205	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
381e4e63 HS	206
381e4e63 HS	207	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	208	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	209	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
381e4e63 HS	210
	211	#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
	212
	213	/*-----------------------------------------------------------------------
	214	* Cache Configuration
	215	*/
	216	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
	217	#if defined(CONFIG_CMD_KGDB)
	218	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	219	#endif
	220
	221	/*-----------------------------------------------------------------------
	222	* SYPCR - System Protection Control 11-9
	223	* SYPCR can only be written once after reset!
	224	*-----------------------------------------------------------------------
	225	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	226	*/
	227	#define CFG_SYPCR 0xffffff89
	228
	229	/*-----------------------------------------------------------------------
	230	* SIUMCR - SIU Module Configuration 11-6
	231	*-----------------------------------------------------------------------
	232	*/
	233	#define CFG_SIUMCR 0x00610480
	234
	235	/*-----------------------------------------------------------------------
	236	* TBSCR - Time Base Status and Control 11-26
	237	*-----------------------------------------------------------------------
	238	* Clear Reference Interrupt Status, Timebase freezing enabled
	239	*/
	240	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	241
	242	/*-----------------------------------------------------------------------
	243	* PISCR - Periodic Interrupt Status and Control 11-31
	244	*-----------------------------------------------------------------------
	245	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	246	*/
	247	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	248
	249	/*-----------------------------------------------------------------------
	250	* SCCR - System Clock and reset Control Register 15-27
	251	*-----------------------------------------------------------------------
	252	* Set clock output, timebase and RTC source and divider,
	253	* power management and some other internal clocks
	254	*/
	255	#define SCCR_MASK 0x01800000
	256	#define CFG_SCCR 0x01800000
	257
	258	#define CFG_DER 0
	259
	260	/*
	261	* Init Memory Controller:
	262	*
	263	* BR0/1 and OR0/1 (FLASH)
	264	*/
	265
	266	#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
	267
	268	/* used to re-map FLASH both when starting from SRAM or FLASH:
	269	* restrict access enough to keep SRAM working (if any)
	270	* but not too much to meddle with FLASH accesses
	271	*/
	272	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	273	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
274
275	/*
276	* FLASH timing: Default value of OR0 after reset
277	*/
278	#define CFG_OR0_PRELIM 0xfe000954
279	#define CFG_BR0_PRELIM 0xf0000401
280
281	/*
282	* BR1 and OR1 (SDRAM)
283	*
284	*/
285	#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
286	#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
287
288	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
289	#define CFG_OR_TIMING_SDRAM 0x00000A00
290
291	#define CFG_OR1_PRELIM 0xfc000800
292	#define CFG_BR1_PRELIM (0x000000C0 \| 0x01)
293
294	#define CFG_MPTPR 0x0200
295	/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
296	1 Write loop Cycle (not used), 1 Timer Loop Cycle */
297	#define CFG_MBMR 0x10964111
298	#define CFG_MAR 0x00000088
299
300	/*
301	* 4096 Rows from SDRAM example configuration
302	* 1000 factor s -> ms
303	* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
304	* 4 Number of refresh cycles per period
305	* 64 Refresh cycle in ms per number of rows
306	*/
307	#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
82afabfe HS	308
	309	/* GPIO/PIGGY on CS3 initialization values
	310	*/
	311	#define CFG_PIGGY_BASE (0x30000000)
	312	#define CFG_OR3_PRELIM (0xfe000d24)
	313	#define CFG_BR3_PRELIM (0x30000401)
381e4e63 HS	314
	315	/*
	316	* Internal Definitions
	317	*
	318	* Boot Flags
	319	*/
	320	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	321	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	322
	323	#define CONFIG_SCC3_ENET
	324	#define CONFIG_ETHPRIME "SCC ETHERNET"
	325	#define CONFIG_HAS_ETH0
	326
	327	/* pass open firmware flat tree */
	328	#define CONFIG_OF_LIBFDT 1
	329	#define CONFIG_OF_BOARD_SETUP 1
	330
	331	#define OF_CPU "PowerPC,866@0"
82afabfe	332	#define OF_SOC "soc@fff00000"
381e4e63 HS	333	#define OF_TBCLK (bd->bi_busfreq / 4)
	334	#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
	335
9661bf9d HS	336	/* enable I2C and select the hardware/software driver */
	337	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	338	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	339	#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
	340	#define CFG_I2C_SLAVE 0x7F
	341	#define I2C_SOFT_DECLARATIONS
	342
	343	/*
	344	* Software (bit-bang) I2C driver configuration
	345	*/
	346	#define I2C_BASE_DIR (CFG_PIGGY_BASE + 0x04)
	347	#define I2C_BASE_PORT (CFG_PIGGY_BASE + 0x09)
	348
	349	#define SDA_BIT 0x40
	350	#define SCL_BIT 0x80
	351	#define SDA_CONF 0x1000
	352	#define SCL_CONF 0x2000
	353
	354	#define I2C_ACTIVE do {} while (0)
	355	#define I2C_TRISTATE do {} while (0)
	356	#define I2C_READ i2c_soft_read_pin ()
	357	#define I2C_SDA(bit) if(bit) { \
	358	(unsigned short )(I2C_BASE_DIR) &= ~SDA_CONF; \
	359	} \
	360	else { \
	361	(unsigned char )(I2C_BASE_PORT) &= ~SDA_BIT; \
	362	(unsigned short )(I2C_BASE_DIR) \|= SDA_CONF; \
	363	}
	364	#define I2C_SCL(bit) if(bit) { \
	365	(unsigned short )(I2C_BASE_DIR) &= ~SCL_CONF; \
	366	} \
	367	else { \
	368	(unsigned char )(I2C_BASE_PORT) &= ~SCL_BIT; \
	369	(unsigned short )(I2C_BASE_DIR) \|= SCL_CONF; \
	370	}
	371	#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
	372
	373	#define CONFIG_I2C_MULTI_BUS 1
	374	#define CONFIG_I2C_CMD_TREE 1
	375	#define CFG_MAX_I2C_BUS 2
	376
f2202450 HS	377	/* EEprom support */
	378	#define CFG_I2C_EEPROM_ADDR_LEN 1
	379	#define CFG_I2C_MULTI_EEPROMS 1
	380	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	381	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	382	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
9661bf9d	383
e5e4edd9 HS	384	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	385	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	386	#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
	387	#define CFG_DTT_MAX_TEMP 70
	388	#define CFG_DTT_LOW_TEMP -30
	389	#define CFG_DTT_HYSTERESIS 3
	390	#define CFG_DTT_BUS_NUM (CFG_MAX_I2C_BUS)
	391
381e4e63	392	#endif /* __CONFIG_H */