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76316a31 | 1 | /* |
4aecfb16 | 2 | * (C) Copyright 2007-2010 Michal Simek |
76316a31 | 3 | * |
cb1bc63b | 4 | * Michal SIMEK <monstr@monstr.eu> |
76316a31 | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
76316a31 MS |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
52a822ed | 12 | #include "../board/xilinx/microblaze-generic/xparameters.h" |
76316a31 | 13 | |
4aecfb16 | 14 | /* MicroBlaze CPU */ |
1a50f164 | 15 | #define MICROBLAZE_V5 1 |
76316a31 | 16 | |
bcec8f49 | 17 | /* linear and spi flash memory */ |
1fe7e8fa SL |
18 | #ifdef XILINX_FLASH_START |
19 | #define FLASH | |
bcec8f49 | 20 | #undef SPIFLASH |
1fe7e8fa SL |
21 | #undef RAMENV /* hold environment in flash */ |
22 | #else | |
bcec8f49 | 23 | #ifdef XILINX_SPI_FLASH_BASEADDR |
1fe7e8fa | 24 | #undef FLASH |
bcec8f49 SL |
25 | #define SPIFLASH |
26 | #undef RAMENV /* hold environment in flash */ | |
27 | #else | |
28 | #undef FLASH | |
29 | #undef SPIFLASH | |
1fe7e8fa SL |
30 | #define RAMENV /* hold environment in RAM */ |
31 | #endif | |
bcec8f49 | 32 | #endif |
1fe7e8fa | 33 | |
76316a31 | 34 | /* uart */ |
af7ae1a4 | 35 | #ifdef XILINX_UARTLITE_BASEADDR |
4aecfb16 MS |
36 | # define CONFIG_XILINX_UARTLITE |
37 | # define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR | |
38 | # define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE | |
39 | # define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } | |
40 | # define CONSOLE_ARG "console=console=ttyUL0,115200\0" | |
e7d591e8 | 41 | #elif XILINX_UART16550_BASEADDR |
4aecfb16 MS |
42 | # define CONFIG_SYS_NS16550 1 |
43 | # define CONFIG_SYS_NS16550_SERIAL | |
1de55ef1 SL |
44 | # if defined(__MICROBLAZEEL__) |
45 | # define CONFIG_SYS_NS16550_REG_SIZE -4 | |
46 | # else | |
47 | # define CONFIG_SYS_NS16550_REG_SIZE 4 | |
48 | # endif | |
4aecfb16 MS |
49 | # define CONFIG_CONS_INDEX 1 |
50 | # define CONFIG_SYS_NS16550_COM1 \ | |
1de55ef1 | 51 | ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) |
4aecfb16 MS |
52 | # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ |
53 | # define CONFIG_BAUDRATE 115200 | |
54 | ||
55 | /* The following table includes the supported baudrates */ | |
56 | # define CONFIG_SYS_BAUDRATE_TABLE \ | |
57 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} | |
58 | # define CONSOLE_ARG "console=console=ttyS0,115200\0" | |
e7d591e8 | 59 | #else |
4aecfb16 | 60 | # error Undefined uart |
af7ae1a4 | 61 | #endif |
76316a31 MS |
62 | |
63 | /* setting reset address */ | |
14d0a02a | 64 | /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ |
76316a31 | 65 | |
17980495 | 66 | /* ethernet */ |
1252df06 | 67 | #undef CONFIG_SYS_ENET |
d1d37b5c | 68 | #if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) |
8422a35e | 69 | # define CONFIG_XILINX_EMACLITE 1 |
4aecfb16 | 70 | # define CONFIG_SYS_ENET |
8422a35e SL |
71 | #endif |
72 | #if defined(XILINX_LLTEMAC_BASEADDR) | |
73 | # define CONFIG_XILINX_LL_TEMAC 1 | |
4aecfb16 | 74 | # define CONFIG_SYS_ENET |
e5845e21 | 75 | #endif |
e634138e MS |
76 | #if defined(XILINX_AXIEMAC_BASEADDR) |
77 | # define CONFIG_XILINX_AXIEMAC 1 | |
78 | # define CONFIG_SYS_ENET | |
79 | #endif | |
330e5545 | 80 | |
e5845e21 | 81 | #undef ET_DEBUG |
17980495 | 82 | |
76316a31 | 83 | /* gpio */ |
4c6a6f02 | 84 | #ifdef XILINX_GPIO_BASEADDR |
4e779ad2 | 85 | # define CONFIG_XILINX_GPIO |
4aecfb16 | 86 | # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR |
4c6a6f02 | 87 | #endif |
76316a31 MS |
88 | |
89 | /* interrupt controller */ | |
4d49b280 | 90 | #ifdef XILINX_INTC_BASEADDR |
4aecfb16 MS |
91 | # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR |
92 | # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS | |
4d49b280 | 93 | #endif |
76316a31 MS |
94 | |
95 | /* timer */ | |
bcbb046b | 96 | #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) |
4aecfb16 MS |
97 | # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR |
98 | # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ | |
4d49b280 | 99 | #endif |
bcbb046b | 100 | |
0f21f98d MS |
101 | /* watchdog */ |
102 | #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) | |
103 | # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR | |
104 | # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ | |
105 | # define CONFIG_HW_WATCHDOG | |
106 | # define CONFIG_XILINX_TB_WATCHDOG | |
107 | #endif | |
108 | ||
e945f6dc | 109 | #ifndef CONFIG_OF_CONTROL |
76316a31 | 110 | /* ddr sdram - main memory */ |
e945f6dc MS |
111 | # define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START |
112 | # define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE | |
113 | #endif | |
114 | ||
115 | #define CONFIG_SYS_MALLOC_LEN 0xC0000 | |
ca7d2266 MS |
116 | #ifndef CONFIG_SPL_BUILD |
117 | # define CONFIG_SYS_MALLOC_F_LEN 1024 | |
118 | #else | |
119 | # define CONFIG_SYS_MALLOC_SIMPLE | |
120 | # define CONFIG_SYS_MALLOC_F_LEN 0x150 | |
121 | #endif | |
e945f6dc MS |
122 | |
123 | /* Stack location before relocation */ | |
124 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_TEXT_BASE | |
76316a31 | 125 | |
8f371b18 SL |
126 | /* |
127 | * CFI flash memory layout - Example | |
128 | * CONFIG_SYS_FLASH_BASE = 0x2200_0000; | |
129 | * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB | |
130 | * | |
131 | * SECT_SIZE = 0x20000; 128kB is one sector | |
132 | * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store | |
133 | * | |
134 | * 0x2200_0000 CONFIG_SYS_FLASH_BASE | |
135 | * FREE 256kB | |
136 | * 0x2204_0000 CONFIG_ENV_ADDR | |
137 | * ENV_AREA 128kB | |
138 | * 0x2206_0000 | |
139 | * FREE | |
140 | * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE | |
141 | * | |
142 | */ | |
143 | ||
76316a31 | 144 | #ifdef FLASH |
4aecfb16 MS |
145 | # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START |
146 | # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE | |
147 | # define CONFIG_SYS_FLASH_CFI 1 | |
148 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
149 | /* ?empty sector */ | |
150 | # define CONFIG_SYS_FLASH_EMPTY_INFO 1 | |
151 | /* max number of memory banks */ | |
152 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
153 | /* max number of sectors on one chip */ | |
154 | # define CONFIG_SYS_MAX_FLASH_SECT 512 | |
155 | /* hardware flash protection */ | |
156 | # define CONFIG_SYS_FLASH_PROTECTION | |
22ff7f4d MS |
157 | /* use buffered writes (20x faster) */ |
158 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
4aecfb16 MS |
159 | # ifdef RAMENV |
160 | # define CONFIG_ENV_IS_NOWHERE 1 | |
161 | # define CONFIG_ENV_SIZE 0x1000 | |
162 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
163 | ||
bcec8f49 | 164 | # else /* FLASH && !RAMENV */ |
4aecfb16 MS |
165 | # define CONFIG_ENV_IS_IN_FLASH 1 |
166 | /* 128K(one sector) for env */ | |
167 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
168 | # define CONFIG_ENV_ADDR \ | |
169 | (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) | |
170 | # define CONFIG_ENV_SIZE 0x20000 | |
bcec8f49 | 171 | # endif /* FLASH && !RAMBOOT */ |
76316a31 | 172 | #else /* !FLASH */ |
bcec8f49 SL |
173 | |
174 | #ifdef SPIFLASH | |
175 | # define CONFIG_SYS_NO_FLASH 1 | |
176 | # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR | |
177 | # define CONFIG_XILINX_SPI 1 | |
178 | # define CONFIG_SPI 1 | |
179 | # define CONFIG_SPI_FLASH 1 | |
180 | # define CONFIG_SPI_FLASH_STMICRO 1 | |
181 | # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 | |
182 | # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ | |
183 | # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS | |
184 | ||
185 | # ifdef RAMENV | |
186 | # define CONFIG_ENV_IS_NOWHERE 1 | |
187 | # define CONFIG_ENV_SIZE 0x1000 | |
188 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
189 | ||
190 | # else /* SPIFLASH && !RAMENV */ | |
191 | # define CONFIG_ENV_IS_IN_SPI_FLASH 1 | |
192 | # define CONFIG_ENV_SPI_MODE SPI_MODE_3 | |
193 | # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
194 | # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
195 | /* 128K(two sectors) for env */ | |
196 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
197 | # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) | |
198 | /* Warning: adjust the offset in respect of other flash content and size */ | |
199 | # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ | |
200 | # endif /* SPIFLASH && !RAMBOOT */ | |
201 | #else /* !SPIFLASH */ | |
202 | ||
4aecfb16 MS |
203 | /* ENV in RAM */ |
204 | # define CONFIG_SYS_NO_FLASH 1 | |
205 | # define CONFIG_ENV_IS_NOWHERE 1 | |
206 | # define CONFIG_ENV_SIZE 0x1000 | |
207 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
bcec8f49 | 208 | #endif /* !SPIFLASH */ |
76316a31 MS |
209 | #endif /* !FLASH */ |
210 | ||
853643d8 MS |
211 | /* system ace */ |
212 | #ifdef XILINX_SYSACE_BASEADDR | |
4aecfb16 MS |
213 | # define CONFIG_SYSTEMACE |
214 | /* #define DEBUG_SYSTEMACE */ | |
215 | # define SYSTEMACE_CONFIG_FPGA | |
216 | # define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR | |
217 | # define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH | |
218 | # define CONFIG_DOS_PARTITION | |
853643d8 MS |
219 | #endif |
220 | ||
e9b737de | 221 | #if defined(XILINX_USE_ICACHE) |
4aecfb16 | 222 | # define CONFIG_ICACHE |
e9b737de | 223 | #else |
4aecfb16 | 224 | # undef CONFIG_ICACHE |
e9b737de MS |
225 | #endif |
226 | ||
227 | #if defined(XILINX_USE_DCACHE) | |
4aecfb16 | 228 | # define CONFIG_DCACHE |
e9b737de | 229 | #else |
4aecfb16 | 230 | # undef CONFIG_DCACHE |
e9b737de MS |
231 | #endif |
232 | ||
5811830f MS |
233 | #ifndef XILINX_DCACHE_BYTE_SIZE |
234 | #define XILINX_DCACHE_BYTE_SIZE 32768 | |
235 | #endif | |
236 | ||
079a136c JL |
237 | /* |
238 | * BOOTP options | |
239 | */ | |
240 | #define CONFIG_BOOTP_BOOTFILESIZE | |
241 | #define CONFIG_BOOTP_BOOTPATH | |
242 | #define CONFIG_BOOTP_GATEWAY | |
243 | #define CONFIG_BOOTP_HOSTNAME | |
76316a31 | 244 | |
5dc11a51 JL |
245 | /* |
246 | * Command line configuration. | |
247 | */ | |
248 | #include <config_cmd_default.h> | |
249 | ||
250 | #define CONFIG_CMD_ASKENV | |
5dc11a51 | 251 | #define CONFIG_CMD_IRQ |
5dc11a51 | 252 | #define CONFIG_CMD_MFSL |
330e5545 | 253 | #define CONFIG_CMD_ECHO |
4e779ad2 | 254 | #define CONFIG_CMD_GPIO |
4d49b280 | 255 | |
e9b737de | 256 | #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) |
4aecfb16 | 257 | # define CONFIG_CMD_CACHE |
e9b737de | 258 | #else |
4aecfb16 | 259 | # undef CONFIG_CMD_CACHE |
e9b737de MS |
260 | #endif |
261 | ||
6d0f6bcf | 262 | #ifndef CONFIG_SYS_ENET |
4aecfb16 | 263 | # undef CONFIG_CMD_NET |
1252df06 | 264 | # undef CONFIG_CMD_NFS |
4d49b280 | 265 | #else |
4aecfb16 MS |
266 | # define CONFIG_CMD_PING |
267 | # define CONFIG_CMD_DHCP | |
4eb29cf0 | 268 | # define CONFIG_CMD_TFTPPUT |
4d49b280 | 269 | #endif |
853643d8 MS |
270 | |
271 | #if defined(CONFIG_SYSTEMACE) | |
4aecfb16 MS |
272 | # define CONFIG_CMD_EXT2 |
273 | # define CONFIG_CMD_FAT | |
853643d8 | 274 | #endif |
5dc11a51 JL |
275 | |
276 | #if defined(FLASH) | |
4aecfb16 MS |
277 | # define CONFIG_CMD_ECHO |
278 | # define CONFIG_CMD_FLASH | |
279 | # define CONFIG_CMD_IMLS | |
280 | # define CONFIG_CMD_JFFS2 | |
7cfb13a7 SL |
281 | # define CONFIG_CMD_UBI |
282 | # undef CONFIG_CMD_UBIFS | |
4aecfb16 | 283 | |
bcec8f49 SL |
284 | # if !defined(RAMENV) |
285 | # define CONFIG_CMD_SAVEENV | |
286 | # define CONFIG_CMD_SAVES | |
287 | # endif | |
288 | ||
289 | #else | |
290 | #if defined(SPIFLASH) | |
291 | # define CONFIG_CMD_SF | |
292 | ||
4aecfb16 MS |
293 | # if !defined(RAMENV) |
294 | # define CONFIG_CMD_SAVEENV | |
295 | # define CONFIG_CMD_SAVES | |
296 | # endif | |
853643d8 | 297 | #else |
4aecfb16 MS |
298 | # undef CONFIG_CMD_IMLS |
299 | # undef CONFIG_CMD_FLASH | |
300 | # undef CONFIG_CMD_JFFS2 | |
2cce2d32 SL |
301 | # undef CONFIG_CMD_UBI |
302 | # undef CONFIG_CMD_UBIFS | |
5dc11a51 | 303 | #endif |
bcec8f49 | 304 | #endif |
76316a31 | 305 | |
5dc11a51 | 306 | #if defined(CONFIG_CMD_JFFS2) |
7cfb13a7 SL |
307 | # define CONFIG_MTD_PARTITIONS |
308 | #endif | |
309 | ||
310 | #if defined(CONFIG_CMD_UBIFS) | |
311 | # define CONFIG_CMD_UBI | |
312 | # define CONFIG_LZO | |
313 | #endif | |
314 | ||
315 | #if defined(CONFIG_CMD_UBI) | |
316 | # define CONFIG_MTD_PARTITIONS | |
317 | # define CONFIG_RBTREE | |
318 | #endif | |
319 | ||
320 | #if defined(CONFIG_MTD_PARTITIONS) | |
321 | /* MTD partitions */ | |
68d7d651 | 322 | #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */ |
942556a9 SR |
323 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
324 | #define CONFIG_FLASH_CFI_MTD | |
c82a541d | 325 | #define MTDIDS_DEFAULT "nor0=flash-0" |
144876a3 MS |
326 | |
327 | /* default mtd partition table */ | |
c82a541d | 328 | #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\ |
144876a3 MS |
329 | "256k(env),3m(kernel),1m(romfs),"\ |
330 | "1m(cramfs),-(jffs2)" | |
331 | #endif | |
332 | ||
76316a31 | 333 | /* Miscellaneous configurable options */ |
6d0f6bcf | 334 | #define CONFIG_SYS_PROMPT "U-Boot-mONStR> " |
4aecfb16 MS |
335 | /* size of console buffer */ |
336 | #define CONFIG_SYS_CBSIZE 512 | |
337 | /* print buffer size */ | |
338 | #define CONFIG_SYS_PBSIZE \ | |
339 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
340 | /* max number of command args */ | |
341 | #define CONFIG_SYS_MAXARGS 15 | |
6d0f6bcf | 342 | #define CONFIG_SYS_LONGHELP |
4aecfb16 MS |
343 | /* default load address */ |
344 | #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START | |
76316a31 | 345 | |
330e5545 | 346 | #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
76316a31 | 347 | #define CONFIG_BOOTARGS "root=romfs" |
330e5545 | 348 | #define CONFIG_HOSTNAME XILINX_BOARD_NAME |
853643d8 | 349 | #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" |
76316a31 | 350 | #define CONFIG_IPADDR 192.168.0.3 |
853643d8 MS |
351 | #define CONFIG_SERVERIP 192.168.0.5 |
352 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
76316a31 MS |
353 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
354 | ||
355 | /* architecture dependent code */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_USR_EXCEP /* user exception */ |
76316a31 | 357 | |
0900bee9 | 358 | #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" |
144876a3 | 359 | |
4aecfb16 | 360 | #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ |
c82a541d SL |
361 | "nor0=flash-0\0"\ |
362 | "mtdparts=mtdparts=flash-0:"\ | |
144876a3 | 363 | "256k(u-boot),256k(env),3m(kernel),"\ |
78376452 MS |
364 | "1m(romfs),1m(cramfs),-(jffs2)\0"\ |
365 | "nc=setenv stdout nc;"\ | |
366 | "setenv stdin nc\0" \ | |
367 | "serial=setenv stdout serial;"\ | |
368 | "setenv stdin serial\0" | |
144876a3 | 369 | |
188dc16b | 370 | #define CONFIG_CMDLINE_EDITING |
188dc16b | 371 | |
78376452 MS |
372 | #define CONFIG_NETCONSOLE |
373 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
374 | ||
0900bee9 MS |
375 | /* Use the HUSH parser */ |
376 | #define CONFIG_SYS_HUSH_PARSER | |
0900bee9 | 377 | |
37e892d9 MS |
378 | /* Enable flat device tree support */ |
379 | #define CONFIG_LMB 1 | |
380 | #define CONFIG_FIT 1 | |
381 | #define CONFIG_OF_LIBFDT 1 | |
382 | ||
8422a35e | 383 | #if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC) |
f5e5e1ff SL |
384 | # define CONFIG_MII 1 |
385 | # define CONFIG_CMD_MII 1 | |
386 | # define CONFIG_PHY_GIGE 1 | |
387 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 | |
388 | # define CONFIG_PHYLIB 1 | |
389 | # define CONFIG_PHY_ATHEROS 1 | |
390 | # define CONFIG_PHY_BROADCOM 1 | |
391 | # define CONFIG_PHY_DAVICOM 1 | |
392 | # define CONFIG_PHY_LXT 1 | |
393 | # define CONFIG_PHY_MARVELL 1 | |
394 | # define CONFIG_PHY_MICREL 1 | |
395 | # define CONFIG_PHY_NATSEMI 1 | |
396 | # define CONFIG_PHY_REALTEK 1 | |
397 | # define CONFIG_PHY_VITESSE 1 | |
398 | #else | |
399 | # undef CONFIG_MII | |
400 | # undef CONFIG_CMD_MII | |
401 | # undef CONFIG_PHYLIB | |
402 | #endif | |
403 | ||
9d242745 | 404 | /* SPL part */ |
9d242745 MS |
405 | #define CONFIG_CMD_SPL |
406 | #define CONFIG_SPL_FRAMEWORK | |
407 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
408 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
409 | #define CONFIG_SPL_SERIAL_SUPPORT | |
410 | #define CONFIG_SPL_BOARD_INIT | |
411 | ||
412 | #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" | |
413 | ||
414 | #define CONFIG_SPL_RAM_DEVICE | |
4dd09742 MS |
415 | #ifdef CONFIG_SYS_FLASH_BASE |
416 | # define CONFIG_SPL_NOR_SUPPORT | |
417 | # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE | |
418 | #endif | |
9d242745 MS |
419 | |
420 | /* for booting directly linux */ | |
421 | #define CONFIG_SPL_OS_BOOT | |
422 | ||
423 | #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ | |
424 | 0x60000) | |
425 | #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ | |
426 | 0x40000) | |
427 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ | |
428 | 0x1000000) | |
429 | ||
430 | /* SP location before relocation, must use scratch RAM */ | |
431 | /* BRAM start */ | |
432 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0 | |
433 | /* BRAM size - will be generated */ | |
ca7d2266 | 434 | #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 |
9d242745 | 435 | |
ca7d2266 MS |
436 | # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
437 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
438 | CONFIG_SYS_MALLOC_F_LEN) | |
9d242745 MS |
439 | |
440 | /* Just for sure that there is a space for stack */ | |
441 | #define CONFIG_SPL_STACK_SIZE 0x100 | |
442 | ||
9d242745 MS |
443 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
444 | ||
445 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ | |
446 | CONFIG_SYS_INIT_RAM_ADDR - \ | |
ca7d2266 | 447 | CONFIG_SYS_MALLOC_F_LEN - \ |
9d242745 MS |
448 | CONFIG_SPL_STACK_SIZE) |
449 | ||
76316a31 | 450 | #endif /* __CONFIG_H */ |