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a14a9446 AD |
1 | /* |
2 | * Copyright 2011 Alex Dubov <oakad@yahoo.com> | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
a14a9446 AD |
5 | */ |
6 | ||
7 | /* | |
8 | * Merury Computers MPQ101 board configuration file | |
9 | * | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | #ifdef CONFIG_36BIT | |
15 | # define CONFIG_PHYS_64BIT | |
16 | #endif | |
17 | ||
18 | /* High Level Configuration Options */ | |
19 | #define CONFIG_BOOKE /* BOOKE */ | |
20 | #define CONFIG_E500 /* BOOKE e500 family */ | |
21 | #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ | |
22 | #define CONFIG_MPC8548 /* MPC8548 specific */ | |
23 | #define CONFIG_MPQ101 /* MPQ101 board specific */ | |
24 | ||
25 | #define CONFIG_SYS_SRIO /* enable serial RapidIO */ | |
26 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
27 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ | |
28 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
29 | ||
30 | /* | |
31 | * These can be toggled for performance analysis, otherwise use default. | |
32 | */ | |
33 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
34 | #define CONFIG_BTB /* toggle branch predition */ | |
35 | ||
36 | #define CONFIG_PANIC_HANG | |
37 | ||
38 | /* | |
39 | * Only possible on E500 Version 2 or newer cores. | |
40 | */ | |
41 | #define CONFIG_ENABLE_36BIT_PHYS | |
42 | ||
43 | #ifdef CONFIG_PHYS_64BIT | |
44 | # define CONFIG_ADDR_MAP | |
45 | # define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
46 | #endif | |
47 | ||
48 | ||
49 | #define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ | |
50 | ||
e46fedfe TT |
51 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
52 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
a14a9446 AD |
53 | |
54 | /* DDR Setup */ | |
55 | #define CONFIG_FSL_DDR2 | |
56 | ||
57 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
58 | ||
59 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
60 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
61 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
62 | ||
63 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
64 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
65 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
66 | ||
67 | /* Fixed 512MB DDR2 parameters */ | |
68 | #define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */ | |
69 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f | |
70 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 | |
71 | #define CONFIG_SYS_DDR_TIMING_3 0x00010000 | |
72 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
73 | #define CONFIG_SYS_DDR_TIMING_1 0x5c47a432 | |
74 | #define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322 | |
75 | #define CONFIG_SYS_DDR_TIMING_2 0x03984cce | |
76 | #define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca | |
77 | #define CONFIG_SYS_DDR_MODE_1 0x00400442 | |
78 | #define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432 | |
79 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
80 | #define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000 | |
81 | #define CONFIG_SYS_DDR_INTERVAL 0x08200100 | |
82 | #define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100 | |
83 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
84 | #define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */ | |
85 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
86 | ||
87 | #define CONFIG_SYS_ALT_MEMTEST | |
88 | #define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */ | |
89 | #define CONFIG_SYS_MEMTEST_END 0x0ffffffc | |
90 | ||
91 | /* | |
92 | * RAM definitions | |
93 | */ | |
94 | #define CONFIG_SYS_INIT_RAM_LOCK | |
95 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
96 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ | |
97 | ||
98 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ | |
99 | - GENERATED_GBL_DATA_SIZE) | |
100 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
101 | ||
102 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
103 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
104 | ||
105 | /* | |
106 | * Local Bus Definitions | |
107 | */ | |
108 | #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ | |
109 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
110 | ||
111 | ||
112 | /* | |
113 | * FLASH on the Local Bus | |
114 | * One bank, 128M, using the CFI driver. | |
115 | */ | |
116 | #define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */ | |
117 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */ | |
118 | ||
119 | #ifdef CONFIG_PHYS_64BIT | |
120 | # define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull | |
121 | #else | |
122 | # define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
123 | #endif | |
124 | ||
125 | /* 0xf8001801 */ | |
126 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | |
127 | | BR_PS_32 | BR_V) | |
128 | ||
129 | /* 0xf8006ff7 */ | |
130 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \ | |
131 | | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ | |
132 | | OR_GPCM_SCY_15 | OR_GPCM_TRLX \ | |
133 | | OR_GPCM_EHTR | OR_GPCM_EAD) | |
134 | ||
135 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
136 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
137 | ||
138 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
139 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
140 | ||
141 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
142 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
143 | ||
144 | #define CONFIG_FLASH_CFI_DRIVER | |
145 | #define CONFIG_SYS_FLASH_CFI | |
146 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
147 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
148 | /* | |
149 | * When initializing flash, if we cannot find the manufacturer ID, | |
150 | * assume this is the AMD flash. | |
151 | */ | |
152 | #define CONFIG_ASSUME_AMD_FLASH | |
153 | ||
154 | /* | |
155 | * Environment parameters | |
156 | */ | |
157 | #define CONFIG_ENV_IS_IN_FLASH | |
158 | #define CONFIG_ENV_OVERWRITE | |
159 | #define CONFIG_SYS_USE_PPCENV | |
160 | #define ENV_IS_EMBEDDED | |
161 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ | |
162 | #define CONFIG_ENV_SIZE 0x800 | |
163 | ||
164 | /* Environment at the start of flash sector, before text. */ | |
165 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE) | |
166 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
167 | #define CONFIG_SYS_TEXT_BASE 0xfffc0800 | |
168 | #define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds" | |
169 | ||
170 | /* | |
171 | * Cypress CY7C67200 USB controller on the Local Bus. | |
172 | * Not supported by u-boot at present. | |
173 | */ | |
174 | #define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 | |
175 | ||
176 | #ifdef CONFIG_PHYS_64BIT | |
177 | # define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull | |
178 | #else | |
179 | # define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE | |
180 | #endif | |
181 | ||
182 | /* 0xf0001001 */ | |
183 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \ | |
184 | | BR_PS_16 | BR_V) | |
185 | ||
186 | /* fffff002 */ | |
187 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \ | |
188 | | OR_GPCM_BCTLD | OR_GPCM_EHTR) | |
189 | ||
190 | /* | |
191 | * Serial Ports | |
192 | */ | |
193 | #define CONFIG_CONS_INDEX 2 | |
194 | #define CONFIG_SYS_NS16550 | |
195 | #define CONFIG_SYS_NS16550_SERIAL | |
196 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
197 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
198 | ||
199 | #define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \ | |
200 | 19200, 38400, 115200} | |
201 | ||
202 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
203 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
204 | ||
205 | /* | |
206 | * I2C buses and peripherals | |
207 | */ | |
208 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
209 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
210 | #define CONFIG_I2C_MULTI_BUS | |
211 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
212 | #define CONFIG_SYS_I2C_SLAVE 0x7f | |
213 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
214 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
215 | ||
216 | /* I2C RTC - M41T81 */ | |
217 | #define CONFIG_RTC_M41T62 | |
218 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
219 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
220 | ||
221 | /* I2C EEPROM - 24C256 */ | |
222 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
223 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
224 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 | |
225 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
226 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
227 | ||
228 | /* | |
229 | * RapidIO MMU | |
230 | */ | |
231 | #ifdef CONFIG_SYS_SRIO | |
232 | # define CONFIG_SRIO1 | |
233 | # define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 | |
234 | # define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
235 | ||
236 | # ifdef CONFIG_PHYS_64BIT | |
237 | # define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull | |
238 | # else | |
239 | # define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT | |
240 | # endif | |
241 | #endif | |
242 | ||
243 | /* | |
244 | * Ethernet | |
245 | */ | |
246 | #ifdef CONFIG_TSEC_ENET | |
247 | ||
a14a9446 AD |
248 | # define CONFIG_MII /* MII PHY management */ |
249 | # define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
250 | ||
251 | # define CONFIG_TSEC1 | |
252 | # define CONFIG_TSEC1_NAME "eTSEC0" | |
253 | # define TSEC1_PHY_ADDR 0x10 | |
254 | # define TSEC1_PHYIDX 0 | |
255 | # define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
256 | ||
257 | # define CONFIG_TSEC2 | |
258 | # define CONFIG_TSEC2_NAME "eTSEC1" | |
259 | # define TSEC2_PHY_ADDR 0x11 | |
260 | # define TSEC2_PHYIDX 0 | |
261 | # define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
262 | ||
263 | # define CONFIG_TSEC3 | |
264 | # define CONFIG_TSEC3_NAME "eTSEC2" | |
265 | # define TSEC3_PHY_ADDR 0x12 | |
266 | # define TSEC3_PHYIDX 0 | |
267 | # define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
268 | ||
269 | # define CONFIG_TSEC4 | |
270 | # define CONFIG_TSEC4_NAME "eTSEC3" | |
271 | # define TSEC4_PHY_ADDR 0x13 | |
272 | # define TSEC4_PHYIDX 0 | |
273 | # define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
274 | ||
275 | /* Options are: eTSEC[0-3] */ | |
276 | # define CONFIG_ETHPRIME "eTSEC0" | |
277 | # define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
278 | #endif | |
279 | ||
280 | /* | |
281 | * Command line configuration. | |
282 | */ | |
283 | #include <config_cmd_default.h> | |
284 | ||
285 | #define CONFIG_CMD_DATE | |
286 | #define CONFIG_CMD_DHCP | |
287 | #define CONFIG_CMD_PING | |
288 | #define CONFIG_CMD_SNTP | |
289 | #define CONFIG_CMD_I2C | |
290 | #define CONFIG_CMD_EEPROM | |
291 | #define CONFIG_CMD_MII | |
292 | #define CONFIG_CMD_ELF | |
293 | #define CONFIG_CMD_IRQ | |
294 | #define CONFIG_CMD_SETEXPR | |
295 | #define CONFIG_CMD_JFFS2 | |
296 | ||
297 | /* | |
298 | * Miscellaneous configurable options | |
299 | */ | |
300 | ||
301 | /* pass open firmware flat tree */ | |
302 | #define CONFIG_OF_LIBFDT | |
303 | #define CONFIG_OF_BOARD_SETUP | |
304 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
305 | ||
306 | #define CONFIG_FIT /* new uImage format support */ | |
307 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
308 | ||
309 | /* Use the HUSH parser */ | |
310 | #define CONFIG_SYS_HUSH_PARSER | |
311 | ||
a14a9446 AD |
312 | |
313 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
314 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
315 | ||
316 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
317 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
318 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
319 | ||
320 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
321 | #define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */ | |
322 | ||
323 | /* Console I/O Buffer Size */ | |
324 | #ifdef CONFIG_CMD_KGDB | |
325 | # define CONFIG_SYS_CBSIZE 1024 | |
326 | #else | |
327 | # define CONFIG_SYS_CBSIZE 256 | |
328 | #endif | |
329 | ||
330 | /* Print Buffer Size */ | |
331 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) | |
332 | ||
333 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
334 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
335 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
336 | ||
337 | /* | |
338 | * For booting Linux, the board info and command line data | |
339 | * have to be in the first 16 MB of memory, since this is | |
340 | * the maximum mapped by the Linux kernel during initialization. | |
341 | */ | |
342 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
343 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ | |
344 | ||
345 | #ifdef CONFIG_CMD_KGDB | |
346 | # define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
347 | # define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
348 | #endif | |
349 | ||
350 | /* | |
351 | * Basic Environment Configuration | |
352 | */ | |
353 | #define CONFIG_BAUDRATE 115200 | |
354 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ | |
355 | ||
356 | /*default location for tftp and bootm*/ | |
357 | #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR | |
358 | ||
359 | #endif /* __CONFIG_H */ |