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3313e0e2 MJ |
1 | /* |
2 | * Configuation settings for MPR2 | |
3 | * | |
4 | * Copyright (C) 2008 | |
5 | * Mark Jonas <mark.jonas@de.bosch.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
3313e0e2 MJ |
8 | */ |
9 | ||
10 | #ifndef __MPR2_H | |
11 | #define __MPR2_H | |
12 | ||
13 | /* Supported commands */ | |
3313e0e2 MJ |
14 | |
15 | /* Default environment variables */ | |
16 | #define CONFIG_BAUDRATE 115200 | |
17 | #define CONFIG_BOOTARGS "console=ttySC0,115200" | |
b3f44c21 | 18 | #define CONFIG_BOOTFILE "/boot/zImage" |
3313e0e2 | 19 | #define CONFIG_LOADADDR 0x8E000000 |
3313e0e2 MJ |
20 | |
21 | /* CPU and platform */ | |
3313e0e2 MJ |
22 | #define CONFIG_CPU_SH7720 1 |
23 | #define CONFIG_MPR2 1 | |
24 | ||
18a40e84 VZ |
25 | #define CONFIG_DISPLAY_BOARDINFO |
26 | ||
3313e0e2 | 27 | /* U-Boot internals */ |
6d0f6bcf | 28 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
29 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
30 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ | |
31 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ | |
32 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ | |
33 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ | |
34 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) | |
35 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
36 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) | |
37 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) | |
3313e0e2 | 38 | |
b8256962 NI |
39 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
40 | ||
3313e0e2 | 41 | /* Memory */ |
6d0f6bcf JCPV |
42 | #define CONFIG_SYS_SDRAM_BASE 0x8C000000 |
43 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
44 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
45 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
3313e0e2 MJ |
46 | |
47 | /* Flash */ | |
6d0f6bcf | 48 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 49 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
50 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
51 | #define CONFIG_SYS_FLASH_BASE 0xA0000000 | |
52 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
53 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
54 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
5a1aceb0 | 55 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
56 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
57 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
6d0f6bcf JCPV |
58 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
59 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
60 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
3313e0e2 MJ |
61 | |
62 | /* Clocks */ | |
63 | #define CONFIG_SYS_CLK_FREQ 24000000 | |
684a501e NI |
64 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
65 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 66 | #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ |
3313e0e2 MJ |
67 | |
68 | /* UART */ | |
6c58a030 | 69 | #define CONFIG_SCIF_CONSOLE 1 |
3313e0e2 MJ |
70 | #define CONFIG_CONS_SCIF0 1 |
71 | ||
72 | #endif /* __MPR2_H */ |