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6c0bbdcc NI |
1 | /* |
2 | * Configuation settings for the Hitachi Solution Engine 7722 | |
3 | * | |
4 | * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
6c0bbdcc NI |
7 | */ |
8 | ||
9 | #ifndef __MS7722SE_H | |
10 | #define __MS7722SE_H | |
11 | ||
6c0bbdcc | 12 | #define CONFIG_CPU_SH7722 1 |
6c0bbdcc | 13 | |
18a40e84 | 14 | #define CONFIG_DISPLAY_BOARDINFO |
6c0bbdcc NI |
15 | #undef CONFIG_SHOW_BOOT_PROGRESS |
16 | ||
17 | /* SMC9111 */ | |
7194ab80 | 18 | #define CONFIG_SMC91111 |
6c0bbdcc NI |
19 | #define CONFIG_SMC91111_BASE (0xB8000000) |
20 | ||
21 | /* MEMORY */ | |
22 | #define MS7722SE_SDRAM_BASE (0x8C000000) | |
23 | #define MS7722SE_FLASH_BASE_1 (0xA0000000) | |
6c0bbdcc NI |
24 | #define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024) |
25 | ||
6d0f6bcf | 26 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
6d0f6bcf | 27 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ |
6c0bbdcc NI |
28 | |
29 | /* SCIF */ | |
6c0bbdcc | 30 | #define CONFIG_CONS_SCIF0 1 |
6c0bbdcc | 31 | |
6d0f6bcf JCPV |
32 | #define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE) |
33 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
6c0bbdcc | 34 | |
6d0f6bcf JCPV |
35 | #undef CONFIG_SYS_ALT_MEMTEST /* Enable alternate, more extensive, memory test */ |
36 | #undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */ | |
6c0bbdcc | 37 | |
6d0f6bcf | 38 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */ |
6c0bbdcc | 39 | |
6d0f6bcf JCPV |
40 | #define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE) |
41 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */ | |
6c0bbdcc | 42 | |
6d0f6bcf | 43 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */ |
6c0bbdcc | 44 | |
6d0f6bcf | 45 | #define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image |
53677ef1 | 46 | in Flash (NOT run time address in SDRAM) ?!? */ |
6d0f6bcf JCPV |
47 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */ |
48 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ | |
6d0f6bcf | 49 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
6c0bbdcc NI |
50 | |
51 | /* FLASH */ | |
6d0f6bcf | 52 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 53 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
54 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
55 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
6c0bbdcc | 56 | |
6d0f6bcf | 57 | #define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */ |
6c0bbdcc | 58 | |
6d0f6bcf | 59 | #define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each |
53677ef1 | 60 | Flash chip */ |
6c0bbdcc NI |
61 | |
62 | /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */ | |
6d0f6bcf JCPV |
63 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 |
64 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \ | |
65 | CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \ | |
6c0bbdcc NI |
66 | } |
67 | ||
6d0f6bcf JCPV |
68 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */ |
69 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */ | |
70 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */ | |
71 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */ | |
6c0bbdcc | 72 | |
6d0f6bcf | 73 | #undef CONFIG_SYS_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */ |
6c0bbdcc | 74 | |
6d0f6bcf | 75 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP |
6c0bbdcc | 76 | |
6c0bbdcc | 77 | #define CONFIG_ENV_OVERWRITE 1 |
0e8d1586 JCPV |
78 | #define CONFIG_ENV_SECT_SIZE (8 * 1024) |
79 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
80 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) |
81 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
0e8d1586 | 82 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
6d0f6bcf | 83 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) |
6c0bbdcc NI |
84 | |
85 | /* Board Clock */ | |
86 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
87 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
88 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 89 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
6c0bbdcc NI |
90 | |
91 | #endif /* __MS7722SE_H */ |