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Commit | Line | Data |
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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
047375bf NI |
2 | /* |
3 | * Configuation settings for the Hitachi Solution Engine 7750 | |
4 | * | |
5 | * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
047375bf NI |
6 | */ |
7 | ||
8 | #ifndef __MS7750SE_H | |
9 | #define __MS7750SE_H | |
69df3c4d | 10 | |
69df3c4d | 11 | #define CONFIG_CPU_SH7750 1 |
047375bf NI |
12 | /* #define CONFIG_CPU_SH7751 1 */ |
13 | /* #define CONFIG_CPU_TYPE_R 1 */ | |
69df3c4d NI |
14 | #define __LITTLE_ENDIAN__ 1 |
15 | ||
18a40e84 VZ |
16 | #define CONFIG_DISPLAY_BOARDINFO |
17 | ||
047375bf NI |
18 | /* |
19 | * Command line configuration. | |
20 | */ | |
69df3c4d | 21 | #define CONFIG_CONS_SCIF1 1 |
69df3c4d | 22 | |
69df3c4d NI |
23 | #define CONFIG_ENV_OVERWRITE 1 |
24 | ||
047375bf | 25 | /* SDRAM */ |
6d0f6bcf JCPV |
26 | #define CONFIG_SYS_SDRAM_BASE (0x8C000000) |
27 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
28 | ||
6d0f6bcf | 29 | #define CONFIG_SYS_PBSIZE 256 |
69df3c4d | 30 | |
6d0f6bcf | 31 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
14d0a02a | 32 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
69df3c4d | 33 | |
047375bf | 34 | /* NOR Flash */ |
6d0f6bcf JCPV |
35 | /* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/ |
36 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) | |
37 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of | |
53677ef1 WD |
38 | * Flash memory banks |
39 | */ | |
6d0f6bcf JCPV |
40 | #define CONFIG_SYS_MAX_FLASH_SECT 142 |
41 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
69df3c4d | 42 | |
6d0f6bcf JCPV |
43 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
44 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */ | |
45 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) | |
46 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ | |
69df3c4d | 47 | |
6d0f6bcf JCPV |
48 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
49 | #define CONFIG_SYS_RX_ETH_BUFFER (8) | |
69df3c4d | 50 | |
6d0f6bcf | 51 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 52 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
53 | #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE |
54 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
55 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
69df3c4d | 56 | |
0e8d1586 JCPV |
57 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
58 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
59 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
60 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
61 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
69df3c4d | 62 | |
047375bf | 63 | /* Board Clock */ |
69df3c4d | 64 | #define CONFIG_SYS_CLK_FREQ 33333333 |
684a501e NI |
65 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
66 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
69df3c4d | 67 | |
047375bf | 68 | #endif /* __MS7750SE_H */ |