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dd4fdc0b WG |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. | |
4 | * | |
5 | * Author: Weijie Gao <weijie.gao@mediatek.com> | |
6 | */ | |
7 | ||
8 | #ifndef __CONFIG_MT7620_H | |
9 | #define __CONFIG_MT7620_H | |
10 | ||
11 | #define CONFIG_SYS_HZ 1000 | |
12 | #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 | |
13 | ||
14 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
15 | ||
16 | #define CONFIG_SYS_MALLOC_LEN 0x100000 | |
17 | #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 | |
18 | ||
19 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 | |
dd4fdc0b WG |
20 | |
21 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 | |
22 | ||
23 | #define CONFIG_SYS_BOOTM_LEN 0x1000000 | |
24 | ||
25 | #define CONFIG_SYS_MAXARGS 16 | |
26 | #define CONFIG_SYS_CBSIZE 1024 | |
27 | ||
28 | /* Serial common */ | |
29 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
30 | ||
31 | /* SPL */ | |
dd4fdc0b WG |
32 | |
33 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE | |
34 | #define CONFIG_SPL_BSS_START_ADDR 0x80010000 | |
35 | #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 | |
36 | #define CONFIG_SPL_MAX_SIZE 0x10000 | |
37 | #define CONFIG_SPL_PAD_TO 0 | |
38 | ||
39 | /* Dummy value */ | |
40 | #define CONFIG_SYS_UBOOT_BASE 0 | |
41 | ||
42 | #endif /* __CONFIG_MT7620_H */ |