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1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Copyright (C) 2020 MediaTek Inc. | |
4 | * | |
5 | * Author: Weijie Gao <weijie.gao@mediatek.com> | |
6 | */ | |
7 | ||
8 | #ifndef __CONFIG_MT7628_H | |
9 | #define __CONFIG_MT7628_H | |
10 | ||
11 | #define CONFIG_SYS_HZ 1000 | |
12 | #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 | |
13 | ||
14 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
15 | ||
16 | #define CONFIG_SYS_MALLOC_LEN 0x100000 | |
17 | #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 | |
18 | ||
19 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 | |
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20 | |
21 | #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 | |
22 | ||
23 | #define CONFIG_SYS_BOOTM_LEN 0x1000000 | |
24 | ||
25 | #define CONFIG_SYS_MAXARGS 16 | |
26 | #define CONFIG_SYS_CBSIZE 1024 | |
27 | ||
28 | /* Serial SPL */ | |
29 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) | |
30 | #define CONFIG_SYS_NS16550_MEM32 | |
31 | #define CONFIG_SYS_NS16550_CLK 40000000 | |
32 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
33 | #define CONFIG_SYS_NS16550_COM1 0xb0000c00 | |
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34 | #endif |
35 | ||
36 | /* Serial common */ | |
37 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ | |
38 | 230400, 460800, 921600 } | |
39 | ||
40 | /* SPL */ | |
6bd888b6 WG |
41 | |
42 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE | |
43 | #define CONFIG_SPL_BSS_START_ADDR 0x80010000 | |
44 | #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 | |
45 | #define CONFIG_SPL_MAX_SIZE 0x10000 | |
46 | #define CONFIG_SPL_PAD_TO 0 | |
47 | ||
48 | /* Dummy value */ | |
49 | #define CONFIG_SYS_UBOOT_BASE 0 | |
50 | ||
51 | #endif /* __CONFIG_MT7628_H */ |