]>
Commit | Line | Data |
---|---|---|
adf22b66 HS |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | ||
32 | #define CONFIG_8260 1 | |
33 | #define CONFIG_MPC8260 1 | |
34 | #define CONFIG_MUAS3001 1 | |
35 | ||
36 | #define CONFIG_CPM2 1 /* Has a CPM2 */ | |
37 | ||
38 | /* Do boardspecific init */ | |
39 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
40 | ||
4a02a2dc HS |
41 | /* enable Watchdog */ |
42 | #define CONFIG_WATCHDOG 1 | |
43 | ||
adf22b66 HS |
44 | /* |
45 | * Select serial console configuration | |
46 | * | |
47 | * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
48 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
49 | * for SCC). | |
50 | */ | |
51 | #define CONFIG_CONS_ON_SMC /* Console is on SMC */ | |
52 | #undef CONFIG_CONS_ON_SCC /* It's not on SCC */ | |
53 | #undef CONFIG_CONS_NONE /* It's not on external UART */ | |
54 | #if defined(CONFIG_MUAS_DEV_BOARD) | |
55 | #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ | |
56 | #else | |
57 | #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ | |
58 | #endif | |
59 | ||
60 | /* | |
61 | * Select ethernet configuration | |
62 | * | |
63 | * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, | |
64 | * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for | |
65 | * SCC, 1-3 for FCC) | |
66 | * | |
67 | * If CONFIG_ETHER_NONE is defined, then either the ethernet routines | |
68 | * must be defined elsewhere (as for the console), or CONFIG_CMD_NET | |
69 | * must be unset. | |
70 | */ | |
71 | #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ | |
72 | #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ | |
73 | #undef CONFIG_ETHER_NONE /* No external Ethernet */ | |
74 | ||
75 | #define CONFIG_ETHER_INDEX 1 | |
76 | #define CONFIG_ETHER_ON_FCC1 | |
3ca55bce | 77 | #define CONFIG_HAS_ETH0 |
adf22b66 HS |
78 | #define FCC_ENET |
79 | ||
80 | /* | |
81 | * - Rx-CLK is CLK11 | |
82 | * - Tx-CLK is CLK12 | |
83 | */ | |
6d0f6bcf JCPV |
84 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) |
85 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) | |
adf22b66 HS |
86 | /* |
87 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
88 | */ | |
6d0f6bcf | 89 | # define CONFIG_SYS_CPMFCR_RAMTYPE (0) |
adf22b66 | 90 | /* know on local Bus */ |
6d0f6bcf | 91 | /* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */ |
adf22b66 HS |
92 | /* |
93 | * - Enable Full Duplex in FSMR | |
94 | */ | |
6d0f6bcf | 95 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
adf22b66 HS |
96 | |
97 | #define CONFIG_MII /* MII PHY management */ | |
98 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
6d0f6bcf | 99 | # define CONFIG_SYS_PHY_ADDR 1 |
adf22b66 HS |
100 | /* |
101 | * GPIO pins used for bit-banged MII communications | |
102 | */ | |
103 | #define MDIO_PORT 0 /* Port A */ | |
be225442 LCM |
104 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
105 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
106 | #define MDC_DECLARE MDIO_DECLARE | |
107 | ||
adf22b66 | 108 | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */ |
110 | #define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */ | |
adf22b66 | 111 | |
6d0f6bcf JCPV |
112 | #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) |
113 | #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) | |
114 | #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) | |
adf22b66 | 115 | |
6d0f6bcf JCPV |
116 | #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ |
117 | else iop->pdat &= ~CONFIG_SYS_MDIO_PIN | |
adf22b66 | 118 | |
6d0f6bcf JCPV |
119 | #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ |
120 | else iop->pdat &= ~CONFIG_SYS_MDC_PIN | |
adf22b66 HS |
121 | |
122 | #define MIIDELAY udelay(1) | |
123 | ||
124 | #ifndef CONFIG_8260_CLKIN | |
125 | #define CONFIG_8260_CLKIN 66000000 /* in Hz */ | |
126 | #endif | |
127 | ||
128 | #define CONFIG_BAUDRATE 115200 | |
129 | ||
130 | /* | |
131 | * Command line configuration. | |
132 | */ | |
133 | #include <config_cmd_default.h> | |
134 | ||
245f6ef3 | 135 | #define CONFIG_CMD_DTT |
adf22b66 HS |
136 | #define CONFIG_CMD_ECHO |
137 | #define CONFIG_CMD_IMMAP | |
138 | #define CONFIG_CMD_MII | |
139 | #define CONFIG_CMD_PING | |
140 | #define CONFIG_CMD_I2C | |
141 | ||
142 | /* | |
143 | * Default environment settings | |
144 | */ | |
145 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
146 | "netdev=eth0\0" \ | |
147 | "u-boot_addr_r=100000\0" \ | |
148 | "kernel_addr_r=200000\0" \ | |
149 | "fdt_addr_r=400000\0" \ | |
150 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
151 | "u-boot=muas3001/u-boot.bin\0" \ | |
152 | "bootfile=muas3001/uImage\0" \ | |
153 | "fdt_file=muas3001/muas3001.dtb\0" \ | |
154 | "ramdisk_file=uRamdisk\0" \ | |
155 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ | |
156 | "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ | |
157 | "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \ | |
158 | "prot on ff000000 ff03ffff\0" \ | |
159 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
160 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
161 | "nfsroot=${serverip}:${rootpath}\0" \ | |
162 | "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ | |
163 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
164 | "addip=setenv bootargs ${bootargs} " \ | |
165 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
166 | "${netmask}:${hostname}:${netdev}:off panic=1\0" \ | |
167 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
168 | "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \ | |
169 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
170 | "net_self=tftp ${kernel_addr_r} ${bootfile}; " \ | |
171 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
172 | "tftp ${ramdisk_addr} ${ramdisk_file}; " \ | |
173 | "run ramargs addip; " \ | |
174 | "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \ | |
175 | "ramdisk_addr=ff210000\0" \ | |
176 | "kernel_addr=ff050000\0" \ | |
177 | "fdt_addr=ff200000\0" \ | |
178 | "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \ | |
179 | " ${ramdisk_addr} ${fdt_addr}\0" \ | |
180 | "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \ | |
181 | " ${ramdisk_file};" \ | |
182 | "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \ | |
183 | "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \ | |
184 | " ${bootfile};" \ | |
185 | "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \ | |
186 | "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \ | |
187 | "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \ | |
188 | "" | |
189 | ||
190 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
191 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
192 | ||
adf22b66 HS |
193 | /* |
194 | * Miscellaneous configurable options | |
195 | */ | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_HUSH_PARSER |
197 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
198 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
199 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
adf22b66 | 200 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 201 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
adf22b66 | 202 | #else |
6d0f6bcf | 203 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
adf22b66 | 204 | #endif |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
206 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
207 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
adf22b66 | 208 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
210 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
adf22b66 | 211 | |
6d0f6bcf | 212 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
adf22b66 | 213 | |
6d0f6bcf | 214 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
adf22b66 | 215 | |
6d0f6bcf | 216 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
adf22b66 | 217 | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
219 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
220 | #define CONFIG_SYS_FLASH_SIZE 32 | |
221 | #define CONFIG_SYS_FLASH_CFI | |
adf22b66 | 222 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
224 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
adf22b66 | 225 | |
6d0f6bcf | 226 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
adf22b66 | 227 | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
229 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
230 | #define CONFIG_SYS_RAMBOOT | |
adf22b66 HS |
231 | #endif |
232 | ||
6d0f6bcf | 233 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ |
adf22b66 | 234 | |
5a1aceb0 | 235 | #define CONFIG_ENV_IS_IN_FLASH |
adf22b66 | 236 | |
5a1aceb0 | 237 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 238 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
6d0f6bcf | 239 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
5a1aceb0 | 240 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
adf22b66 HS |
241 | |
242 | /* | |
243 | * I2C Bus | |
244 | */ | |
245 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
247 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
adf22b66 | 248 | |
6d0f6bcf | 249 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
245f6ef3 HS |
250 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
251 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
252 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
254 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
255 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
245f6ef3 | 256 | |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_IMMR 0xF0000000 |
258 | #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 | |
adf22b66 | 259 | |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
261 | #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ | |
262 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
263 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
264 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
adf22b66 HS |
265 | |
266 | /* Hard reset configuration word */ | |
6d0f6bcf | 267 | #define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */ |
adf22b66 HS |
268 | |
269 | /* No slaves */ | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
271 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
272 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
273 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
274 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
275 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
276 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
adf22b66 HS |
277 | |
278 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
279 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
280 | ||
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ |
282 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
adf22b66 | 283 | |
6d0f6bcf | 284 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ |
adf22b66 | 285 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 286 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
adf22b66 HS |
287 | #endif |
288 | ||
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_HID0_INIT 0 |
290 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) | |
adf22b66 | 291 | |
6d0f6bcf | 292 | #define CONFIG_SYS_HID2 0 |
adf22b66 | 293 | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_SIUMCR 0x00200000 |
295 | #define CONFIG_SYS_BCR 0x004c0000 | |
296 | #define CONFIG_SYS_SCCR 0x0 | |
adf22b66 | 297 | |
4a02a2dc HS |
298 | /*----------------------------------------------------------------------- |
299 | * SYPCR - System Protection Control 4-35 | |
300 | * SYPCR can only be written once after reset! | |
301 | *----------------------------------------------------------------------- | |
302 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
303 | */ | |
304 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 305 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
4a02a2dc HS |
306 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
307 | #else | |
6d0f6bcf | 308 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
4a02a2dc HS |
309 | SYPCR_SWRI|SYPCR_SWP) |
310 | #endif /* CONFIG_WATCHDOG */ | |
311 | ||
adf22b66 HS |
312 | /*----------------------------------------------------------------------- |
313 | * RMR - Reset Mode Register 5-5 | |
314 | *----------------------------------------------------------------------- | |
315 | * turn on Checkstop Reset Enable | |
316 | */ | |
6d0f6bcf | 317 | #define CONFIG_SYS_RMR 0 |
adf22b66 HS |
318 | |
319 | /*----------------------------------------------------------------------- | |
320 | * TMCNTSC - Time Counter Status and Control 4-40 | |
321 | *----------------------------------------------------------------------- | |
322 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
323 | * and enable Time Counter | |
324 | */ | |
6d0f6bcf | 325 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
adf22b66 HS |
326 | |
327 | /*----------------------------------------------------------------------- | |
328 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
329 | *----------------------------------------------------------------------- | |
330 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
331 | * Periodic timer | |
332 | */ | |
6d0f6bcf | 333 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
adf22b66 HS |
334 | |
335 | /*----------------------------------------------------------------------- | |
336 | * RCCR - RISC Controller Configuration 13-7 | |
337 | *----------------------------------------------------------------------- | |
338 | */ | |
6d0f6bcf | 339 | #define CONFIG_SYS_RCCR 0 |
adf22b66 HS |
340 | |
341 | /* | |
342 | * Init Memory Controller: | |
343 | * | |
344 | * Bank Bus Machine PortSz Device | |
345 | * ---- --- ------- ------ ------ | |
346 | * 0 60x GPCM 32 bit FLASH | |
347 | * 1 60x SDRAM 64 bit SDRAM | |
348 | * 4 60x GPCM 16 bit I/O Ctrl | |
349 | * | |
350 | */ | |
351 | /* Bank 0 - FLASH | |
352 | */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
adf22b66 HS |
354 | BRx_PS_32 |\ |
355 | BRx_MS_GPCM_P |\ | |
356 | BRx_V) | |
357 | ||
6d0f6bcf | 358 | #define CONFIG_SYS_OR0_PRELIM (0xff000020) |
adf22b66 HS |
359 | |
360 | /* Bank 1 - 60x bus SDRAM | |
361 | */ | |
6d0f6bcf | 362 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ |
adf22b66 | 363 | |
6d0f6bcf | 364 | #define CONFIG_SYS_MPTPR 0x2800 |
adf22b66 HS |
365 | |
366 | /*----------------------------------------------------------------------------- | |
367 | * Address for Mode Register Set (MRS) command | |
368 | *----------------------------------------------------------------------------- | |
369 | */ | |
6d0f6bcf JCPV |
370 | #define CONFIG_SYS_MRS_OFFS 0x00000110 |
371 | #define CONFIG_SYS_PSRT 0x13 | |
adf22b66 | 372 | |
6d0f6bcf | 373 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ |
adf22b66 HS |
374 | BRx_PS_64 |\ |
375 | BRx_MS_SDRAM_P |\ | |
376 | BRx_V) | |
377 | ||
6d0f6bcf | 378 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE |
adf22b66 HS |
379 | |
380 | /* SDRAM initialization values | |
381 | */ | |
6d0f6bcf | 382 | #define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
adf22b66 HS |
383 | ORxS_BPD_4 |\ |
384 | ORxS_ROWST_PBI1_A7 |\ | |
385 | ORxS_NUMR_12) | |
386 | ||
6d0f6bcf | 387 | #define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3 |
a55d074d | 388 | |
6d0f6bcf | 389 | #define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
a55d074d HS |
390 | ORxS_BPD_4 |\ |
391 | ORxS_ROWST_PBI1_A4 |\ | |
392 | ORxS_NUMR_12) | |
393 | ||
6d0f6bcf | 394 | #define CONFIG_SYS_PSDMR_BIG 0x014f36a3 |
adf22b66 HS |
395 | |
396 | /* IO on CS4 initialization values | |
397 | */ | |
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_IO_BASE 0xc0000000 |
399 | #define CONFIG_SYS_IO_SIZE 1 | |
adf22b66 | 400 | |
6d0f6bcf | 401 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\ |
0b7c5639 | 402 | BRx_PS_16 | BRx_MS_GPCM_L | BRx_V) |
adf22b66 | 403 | |
6d0f6bcf | 404 | #define CONFIG_SYS_OR4_PRELIM (0xfff80020) |
adf22b66 | 405 | |
6d0f6bcf | 406 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
adf22b66 HS |
407 | |
408 | /* pass open firmware flat tree */ | |
409 | #define CONFIG_OF_LIBFDT 1 | |
410 | #define CONFIG_OF_BOARD_SETUP 1 | |
411 | ||
adf22b66 HS |
412 | #define OF_TBCLK (bd->bi_busfreq / 4) |
413 | #if defined(CONFIG_MUAS_DEV_BOARD) | |
414 | #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" | |
415 | #else | |
416 | #define OF_STDOUT_PATH "/soc/cpm/serial@11a80" | |
417 | #endif | |
418 | ||
419 | #endif /* __CONFIG_H */ |