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5fb2b234 HS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5fb2b234 HS |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | /* | |
11 | * High Level Configuration Options | |
12 | * (easy to change) | |
13 | */ | |
b2a6dfe4 | 14 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
5fb2b234 HS |
15 | #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ |
16 | #define CONFIG_MUNICES 1 /* ... on MUNICes board */ | |
2ae18241 WD |
17 | |
18 | #ifndef CONFIG_SYS_TEXT_BASE | |
19 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
20 | #endif | |
21 | ||
6d0f6bcf | 22 | #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ |
6d0f6bcf | 23 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
31d82672 | 24 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
5fb2b234 HS |
25 | |
26 | /* | |
27 | * Command line configuration. | |
28 | */ | |
5fb2b234 HS |
29 | #define CONFIG_CMD_REGINFO |
30 | ||
1b769881 | 31 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 32 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
5fb2b234 HS |
33 | #endif |
34 | ||
35 | /* | |
36 | * Serial console configuration | |
37 | */ | |
38 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
6d0f6bcf | 39 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
5fb2b234 HS |
40 | |
41 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ | |
5fb2b234 HS |
42 | #undef CONFIG_BOOTARGS |
43 | ||
44 | #define CONFIG_PREBOOT "echo;" \ | |
45 | "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \ | |
46 | "echo" | |
47 | ||
48 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
49 | "netdev=eth0\0" \ | |
50 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
51 | "nfsroot=$(serverip):$(rootpath)\0" \ | |
52 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
53 | "addip=setenv bootargs $(bootargs) " \ | |
54 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
55 | ":$(hostname):$(netdev):off panic=5\0" \ | |
56 | "flash_nfs=run nfsargs addip;" \ | |
57 | "bootm $(kernel_addr)\0" \ | |
58 | "flash_self=run ramargs addip;" \ | |
59 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
60 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ | |
61 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
62 | "bootfile=/tftpboot/munices/u-boot.bin\0" \ | |
63 | "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \ | |
64 | "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \ | |
65 | "" | |
66 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
67 | ||
68 | /* | |
69 | * IPB Bus clocking configuration. | |
70 | */ | |
6d0f6bcf JCPV |
71 | #define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ |
72 | #if defined(CONFIG_SYS_IPBSPEED_133) | |
5fb2b234 HS |
73 | /* |
74 | * PCI Bus clocking configuration | |
75 | * | |
76 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 77 | * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't |
5fb2b234 HS |
78 | * been tested with a IPB Bus Clock of 66 MHz. |
79 | */ | |
6d0f6bcf | 80 | #define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */ |
5fb2b234 | 81 | #else |
6d0f6bcf | 82 | #undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */ |
5fb2b234 HS |
83 | #endif |
84 | ||
85 | /* | |
86 | * Memory map | |
87 | */ | |
6d0f6bcf | 88 | #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ |
fa05664c | 89 | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
91 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
5fb2b234 | 92 | /* Use SRAM until RAM will be available */ |
6d0f6bcf | 93 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 94 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
25ddd1fb | 95 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
97 | ||
14d0a02a | 98 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
99 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
100 | # define CONFIG_SYS_RAMBOOT 1 | |
5fb2b234 HS |
101 | #endif |
102 | ||
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
104 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
105 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
5fb2b234 HS |
106 | |
107 | /* | |
108 | * Flash configuration | |
109 | */ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
111 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
00b1883a | 112 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
114 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
115 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */ | |
116 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
117 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ | |
118 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
5fb2b234 HS |
119 | |
120 | /* | |
121 | * Chip selects configuration | |
122 | */ | |
123 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
125 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
126 | #define CONFIG_SYS_BOOTCS_CFG 0x00047800 | |
5fb2b234 HS |
127 | |
128 | /* | |
129 | * Environment settings | |
130 | */ | |
5a1aceb0 | 131 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 132 | #define CONFIG_ENV_OFFSET 0x40000 |
14d0a02a | 133 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET) |
0e8d1586 JCPV |
134 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
135 | #define CONFIG_ENV_SIZE 0x4000 | |
136 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) | |
14d0a02a | 137 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND) |
0e8d1586 | 138 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
5fb2b234 HS |
139 | #define CONFIG_ENV_OVERWRITE 1 |
140 | ||
141 | /* | |
142 | * Ethernet configuration | |
143 | */ | |
144 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 145 | #define CONFIG_MPC5xxx_FEC_MII100 |
5fb2b234 HS |
146 | #define CONFIG_PHY_ADDR 0x01 |
147 | #define CONFIG_MII 1 | |
148 | ||
149 | /* | |
150 | * GPIO configuration | |
151 | */ | |
6d0f6bcf | 152 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD |
5fb2b234 HS |
153 | no PCI */ |
154 | ||
155 | /* | |
156 | * Miscellaneous configurable options | |
157 | */ | |
6d0f6bcf | 158 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
160 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
161 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
162 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5fb2b234 | 163 | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
165 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
5fb2b234 | 166 | |
6d0f6bcf | 167 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
5fb2b234 | 168 | |
5fb2b234 HS |
169 | #define CONFIG_CMDLINE_EDITING 1 |
170 | ||
171 | /* | |
172 | * Various low-level settings | |
173 | */ | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
175 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
5fb2b234 | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_CS_BURST 0x00000000 |
178 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
179 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 | |
5fb2b234 | 180 | |
5fb2b234 HS |
181 | #define OF_CPU "PowerPC,5200@0" |
182 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
183 | #define OF_SOC "soc5200@f0000000" | |
184 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
185 | ||
186 | #endif /* __CONFIG_H */ |