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5fb2b234 HS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5fb2b234 HS |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | /* | |
11 | * High Level Configuration Options | |
12 | * (easy to change) | |
13 | */ | |
b2a6dfe4 | 14 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
5fb2b234 HS |
15 | #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ |
16 | #define CONFIG_MUNICES 1 /* ... on MUNICes board */ | |
2ae18241 WD |
17 | |
18 | #ifndef CONFIG_SYS_TEXT_BASE | |
19 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
20 | #endif | |
21 | ||
6d0f6bcf | 22 | #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ |
6d0f6bcf | 23 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
31d82672 | 24 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
5fb2b234 HS |
25 | |
26 | /* | |
27 | * Command line configuration. | |
28 | */ | |
29 | #include <config_cmd_default.h> | |
30 | ||
31 | #define CONFIG_CMD_ASKENV | |
32 | #define CONFIG_CMD_ELF | |
33 | #define CONFIG_CMD_IMMAP | |
34 | #define CONFIG_CMD_NET | |
35 | #define CONFIG_CMD_PING | |
36 | #define CONFIG_CMD_REGINFO | |
37 | ||
1b769881 | 38 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 39 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
5fb2b234 HS |
40 | #endif |
41 | ||
42 | /* | |
43 | * Serial console configuration | |
44 | */ | |
45 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
46 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 47 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
5fb2b234 HS |
48 | |
49 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ | |
50 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
51 | #undef CONFIG_BOOTARGS | |
52 | ||
53 | #define CONFIG_PREBOOT "echo;" \ | |
54 | "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \ | |
55 | "echo" | |
56 | ||
57 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
58 | "netdev=eth0\0" \ | |
59 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
60 | "nfsroot=$(serverip):$(rootpath)\0" \ | |
61 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
62 | "addip=setenv bootargs $(bootargs) " \ | |
63 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
64 | ":$(hostname):$(netdev):off panic=5\0" \ | |
65 | "flash_nfs=run nfsargs addip;" \ | |
66 | "bootm $(kernel_addr)\0" \ | |
67 | "flash_self=run ramargs addip;" \ | |
68 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
69 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ | |
70 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
71 | "bootfile=/tftpboot/munices/u-boot.bin\0" \ | |
72 | "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \ | |
73 | "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \ | |
74 | "" | |
75 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
76 | ||
77 | /* | |
78 | * IPB Bus clocking configuration. | |
79 | */ | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ |
81 | #if defined(CONFIG_SYS_IPBSPEED_133) | |
5fb2b234 HS |
82 | /* |
83 | * PCI Bus clocking configuration | |
84 | * | |
85 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 86 | * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't |
5fb2b234 HS |
87 | * been tested with a IPB Bus Clock of 66 MHz. |
88 | */ | |
6d0f6bcf | 89 | #define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */ |
5fb2b234 | 90 | #else |
6d0f6bcf | 91 | #undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */ |
5fb2b234 HS |
92 | #endif |
93 | ||
94 | /* | |
95 | * Memory map | |
96 | */ | |
6d0f6bcf | 97 | #define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ |
fa05664c | 98 | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
100 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
5fb2b234 | 101 | /* Use SRAM until RAM will be available */ |
6d0f6bcf | 102 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 103 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
25ddd1fb | 104 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
106 | ||
14d0a02a | 107 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
108 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
109 | # define CONFIG_SYS_RAMBOOT 1 | |
5fb2b234 HS |
110 | #endif |
111 | ||
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
113 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
114 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
5fb2b234 HS |
115 | |
116 | /* | |
117 | * Flash configuration | |
118 | */ | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
120 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
00b1883a | 121 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
123 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
124 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */ | |
125 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
126 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ | |
127 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
5fb2b234 HS |
128 | |
129 | /* | |
130 | * Chip selects configuration | |
131 | */ | |
132 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
134 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
135 | #define CONFIG_SYS_BOOTCS_CFG 0x00047800 | |
5fb2b234 HS |
136 | |
137 | /* | |
138 | * Environment settings | |
139 | */ | |
5a1aceb0 | 140 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 141 | #define CONFIG_ENV_OFFSET 0x40000 |
14d0a02a | 142 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET) |
0e8d1586 JCPV |
143 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
144 | #define CONFIG_ENV_SIZE 0x4000 | |
145 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) | |
14d0a02a | 146 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND) |
0e8d1586 | 147 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
5fb2b234 HS |
148 | #define CONFIG_ENV_OVERWRITE 1 |
149 | ||
150 | /* | |
151 | * Ethernet configuration | |
152 | */ | |
153 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 154 | #define CONFIG_MPC5xxx_FEC_MII100 |
5fb2b234 HS |
155 | #define CONFIG_PHY_ADDR 0x01 |
156 | #define CONFIG_MII 1 | |
157 | ||
158 | /* | |
159 | * GPIO configuration | |
160 | */ | |
6d0f6bcf | 161 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD |
5fb2b234 HS |
162 | no PCI */ |
163 | ||
164 | /* | |
165 | * Miscellaneous configurable options | |
166 | */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
169 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
170 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
171 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5fb2b234 | 172 | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
174 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
5fb2b234 | 175 | |
6d0f6bcf | 176 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
5fb2b234 HS |
177 | |
178 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
179 | #define CONFIG_CMDLINE_EDITING 1 | |
180 | ||
181 | /* | |
182 | * Various low-level settings | |
183 | */ | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
185 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
5fb2b234 | 186 | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_CS_BURST 0x00000000 |
188 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
189 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 | |
5fb2b234 HS |
190 | |
191 | /* pass open firmware flat tree */ | |
192 | #define CONFIG_OF_LIBFDT 1 | |
193 | #define CONFIG_OF_BOARD_SETUP 1 | |
194 | ||
195 | #define OF_CPU "PowerPC,5200@0" | |
196 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
197 | #define OF_SOC "soc5200@f0000000" | |
198 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
199 | ||
200 | #endif /* __CONFIG_H */ |