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1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | /* | |
27 | * High Level Configuration Options | |
28 | * (easy to change) | |
29 | */ | |
30 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
31 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
32 | #define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ | |
33 | #define CONFIG_MUNICES 1 /* ... on MUNICes board */ | |
34 | #define CFG_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ | |
35 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
36 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
37 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ | |
38 | ||
39 | /* | |
40 | * Command line configuration. | |
41 | */ | |
42 | #include <config_cmd_default.h> | |
43 | ||
44 | #define CONFIG_CMD_ASKENV | |
45 | #define CONFIG_CMD_ELF | |
46 | #define CONFIG_CMD_IMMAP | |
47 | #define CONFIG_CMD_NET | |
48 | #define CONFIG_CMD_PING | |
49 | #define CONFIG_CMD_REGINFO | |
50 | ||
1b769881 | 51 | #if defined(CONFIG_CMD_KGDB) |
5fb2b234 HS |
52 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
53 | #endif | |
54 | ||
55 | /* | |
56 | * Serial console configuration | |
57 | */ | |
58 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
59 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
60 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
61 | ||
62 | #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ | |
63 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
64 | #undef CONFIG_BOOTARGS | |
65 | ||
66 | #define CONFIG_PREBOOT "echo;" \ | |
67 | "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \ | |
68 | "echo" | |
69 | ||
70 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
71 | "netdev=eth0\0" \ | |
72 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
73 | "nfsroot=$(serverip):$(rootpath)\0" \ | |
74 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
75 | "addip=setenv bootargs $(bootargs) " \ | |
76 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ | |
77 | ":$(hostname):$(netdev):off panic=5\0" \ | |
78 | "flash_nfs=run nfsargs addip;" \ | |
79 | "bootm $(kernel_addr)\0" \ | |
80 | "flash_self=run ramargs addip;" \ | |
81 | "bootm $(kernel_addr) $(ramdisk_addr)\0" \ | |
82 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ | |
83 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
84 | "bootfile=/tftpboot/munices/u-boot.bin\0" \ | |
85 | "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \ | |
86 | "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \ | |
87 | "" | |
88 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
89 | ||
90 | /* | |
91 | * IPB Bus clocking configuration. | |
92 | */ | |
93 | #define CFG_IPBSPEED_133 /* define for 133MHz speed */ | |
94 | #if defined(CFG_IPBSPEED_133) | |
95 | /* | |
96 | * PCI Bus clocking configuration | |
97 | * | |
98 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
99 | * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't | |
100 | * been tested with a IPB Bus Clock of 66 MHz. | |
101 | */ | |
102 | #define CFG_PCISPEED_66 /* define for 66MHz speed */ | |
103 | #else | |
104 | #undef CFG_PCISPEED_66 /* for 33MHz speed */ | |
105 | #endif | |
106 | ||
107 | /* | |
108 | * Memory map | |
109 | */ | |
110 | #define CFG_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ | |
fa05664c HS |
111 | |
112 | #define CFG_DEFAULT_MBAR 0x80000000 | |
5fb2b234 HS |
113 | #define CFG_SDRAM_BASE 0x00000000 |
114 | /* Use SRAM until RAM will be available */ | |
115 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
116 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
117 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
118 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
119 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
120 | ||
121 | #define CFG_MONITOR_BASE TEXT_BASE | |
122 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
123 | # define CFG_RAMBOOT 1 | |
124 | #endif | |
125 | ||
126 | #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ | |
127 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
128 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
129 | ||
130 | /* | |
131 | * Flash configuration | |
132 | */ | |
133 | #define CFG_FLASH_BASE 0xFF000000 | |
134 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
135 | #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
5fb2b234 HS |
136 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
137 | #define CFG_FLASH_EMPTY_INFO | |
138 | #define CFG_FLASH_SIZE 0x01000000 /* 16 MByte */ | |
139 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
140 | #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ | |
141 | #define CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
142 | ||
143 | /* | |
144 | * Chip selects configuration | |
145 | */ | |
146 | /* Boot Chipselect */ | |
147 | #define CFG_BOOTCS_START CFG_FLASH_BASE | |
148 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
149 | #define CFG_BOOTCS_CFG 0x00047800 | |
150 | ||
151 | /* | |
152 | * Environment settings | |
153 | */ | |
154 | #define CFG_ENV_IS_IN_FLASH 1 | |
155 | #define CFG_ENV_OFFSET 0x40000 | |
156 | #define CFG_ENV_ADDR (TEXT_BASE + CFG_ENV_OFFSET) | |
157 | #define CFG_ENV_SECT_SIZE 0x20000 | |
158 | #define CFG_ENV_SIZE 0x4000 | |
159 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SECT_SIZE) | |
160 | #define CFG_ENV_ADDR_REDUND (TEXT_BASE + CFG_ENV_OFFSET_REDUND) | |
161 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
162 | #define CONFIG_ENV_OVERWRITE 1 | |
163 | ||
164 | /* | |
165 | * Ethernet configuration | |
166 | */ | |
167 | #define CONFIG_MPC5xxx_FEC 1 | |
168 | #define CONFIG_PHY_ADDR 0x01 | |
169 | #define CONFIG_MII 1 | |
170 | ||
171 | /* | |
172 | * GPIO configuration | |
173 | */ | |
174 | #define CFG_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD | |
175 | no PCI */ | |
176 | ||
177 | /* | |
178 | * Miscellaneous configurable options | |
179 | */ | |
180 | #define CFG_LONGHELP /* undef to save memory */ | |
181 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
182 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
183 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
184 | #define CFG_MAXARGS 16 /* max number of command args */ | |
185 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
186 | ||
187 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
188 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
189 | ||
190 | #define CFG_LOAD_ADDR 0x200000 /* default load address */ | |
191 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
192 | ||
193 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
194 | #define CONFIG_CMDLINE_EDITING 1 | |
195 | ||
196 | /* | |
197 | * Various low-level settings | |
198 | */ | |
199 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
200 | #define CFG_HID0_FINAL HID0_ICE | |
201 | ||
202 | #define CFG_CS_BURST 0x00000000 | |
203 | #define CFG_CS_DEADCYCLE 0x33333333 | |
204 | #define CFG_RESET_ADDRESS 0xff000000 | |
205 | ||
206 | /* pass open firmware flat tree */ | |
207 | #define CONFIG_OF_LIBFDT 1 | |
208 | #define CONFIG_OF_BOARD_SETUP 1 | |
209 | ||
210 | #define OF_CPU "PowerPC,5200@0" | |
211 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
212 | #define OF_SOC "soc5200@f0000000" | |
213 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
214 | ||
215 | #endif /* __CONFIG_H */ |